DATASHEET
SET-TOP CLOCK SOURCE
Description
The MK2761A is a low-cost, low-jitter, high-performance
clock synthesizer for set-top box applications. Using analog
Phase-Locked Loop (PLL) techniques, the device accepts a
27 MHz crystal or clock input to produce multiple output
clocks including the processor clock, the UART clock, a
selectable audio clock, and four low skew copies of the 27
MHz. The audio clocks are frequency-locked to the 27 MHz
using our patented zero ppm error techniques. This allows
audio and video to track exactly, thereby eliminating the
need for large buffer memory.
IDT manufactures a large variety of Set-top Box and
multimedia clock synthesizers for all applications. Consult
IDT to eliminate crystals and oscillators from your board.
MK2761A
Features
•
Packaged in a 16-pin narrow (150 mil) SOIC
•
Pb (lead) free package
•
Selectable audio sampling frequencies support 32, 44.1,
and 48 kHz in most DACs
•
•
•
•
•
•
•
27 MHz crystal or clock input
Processor frequency of 16.67 MHz
Fixed clocks of 27 and 3.6864 MHz
Zero ppm in audio clocks exactly track video frequency
25 mA output drive capability at TTL levels
Advanced, low-power, sub-micron CMOS process
Operating voltage of 5.0 V ±10%
Block Diagram
VDD
2
ACS1:0
27.000 MHz
crystal or clock
X1
2
Clock
Synthesis and
Control
Circuitry
Audio Clock
3.6864 MHz
16.667 MHz
Crystal
Ocsillator
X2
3
GND
4
27.000 MHz
IDT™
SET-TOP CLOCK SOURCE
1
MK2761A
REV F 051310
MK2761A
SET-TOP CLOCK SOURCE
CLOCK SYNTHESIZER
Pin Assignment
ACS1
X2
X1/ICLK
VDD
GND
16.67 MHz
3.68 MHz
ACLK
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
ACS0
27 MHz
27 MHz
VDD
GND
27 MHz
27 MHz
GND
Audio Clock (MHz) DecodingTable
ACS1
0
0
1
1
ACS0
0
1
0
1
ACLK
8.192
11.2896
12.288
5.6448
16-pin (150 mil) SOIC
Pin Descriptions
Pin
Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Pin
Name
ACS1
X2
X1/ICLK
VDD
GND
16.67M
3.68M
ACLK
GND
27M
27M
GND
VDD
27M
27M
ACS0
Pin
Type
Input
XO
XI
Power
Power
Output
Output
Output
Power
Output
Output
Power
Power
Output
Output
Input
Pin Description
Audio clock Select 1. Selects ACLK on pin 8. See table above.
Crystal connection. Connect to 27 MHz crystal. Leave unconnected for clock
input.
Crystal connection. Connect to 27 MHz crystal or to a 27 MHz input clock.
Connect to +5 V.
Connect to ground.
16.667 MHz processor clock output.
3.6864 MHz clock output.
Audio clock output. Determined by status of ACS1, ACS0. See table above
Connect to ground.
27 MHz buffered reference clock output. Duty cycle matches input clock.
27 MHz buffered reference clock output. Duty cycle matches input clock.
Connect to ground.
Connect to +5 V.
27 MHz buffered reference clock output. Duty cycle matches input clock.
27 MHz buffered reference clock output. Duty cycle matches input clock.
Audio clock Select 0. Selects audio clock on pin 8. See table above.
IDT™
SET-TOP CLOCK SOURCE
2
MK2761A
REV F 051310
MK2761A
SET-TOP CLOCK SOURCE
CLOCK SYNTHESIZER
External Components
The MK2761A requires a minimum number of external components for proper operation. Decoupling capacitors of
0.1µF should be connected between VDD and GND, as close to the MK2761A as possible. A series termination
resistor of 33Ω may be used for each clock output. If a clock input is not used, the 27 MHz crystal must be
connected as close to the chip as possible. The crystal should be a fundamental mode (do not use third overtone),
parallel resonant, 50 ppm or better. Crystal capacitors should be connected from pins X1 to ground and X2 to
ground. The value of these capacitors is given by the following equation, where CL is the crystal load capacitance:
Crystal caps (pF) = (CL-4) x 2. So, for a crystal with 16 pF load capacitance, the crystal caps should be 24 pF each.
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the MK2761A. These ratings, which are
standard values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these
or any other conditions above those indicated in the operational sections of the specifications is not implied.
Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical
parameters are guaranteed only over the recommended operating temperature range.
Item
Supply Voltage, VDD
All Inputs and Outputs
Ambient Operating Temperature
Storage Temperature
Junction Temperature
Soldering Temperature
7V
Rating
-0.5 V to VDD+0.5 V
0 to +70° C
-65 to +150° C
125° C
260° C
Recommended Operation Conditions
Parameter
Ambient Operating Temperature
Power Supply Voltage (measured in respect to GND)
Min.
0
+4.5
Typ.
Max.
+70
+5.5
Units
°
C
V
IDT™
SET-TOP CLOCK SOURCE
3
MK2761A
REV F 051310
MK2761A
SET-TOP CLOCK SOURCE
CLOCK SYNTHESIZER
DC Electrical Characteristics
VDD = 5.0 V ±10%
(unless otherwise noted), Temp 0 to +70°
C
Parameter
Operating Voltage
Input High Voltage
Input Low Voltage
Input High Voltage
Input Low Voltage
Output High Voltage
Output Low Voltage
Output High Voltage, CMOS
level
Operating Supply Current
Short Circuit Current
Input Capacitance
Frequency Error, ACLK
Symbol
VDD
V
IH
V
IL
V
IH
V
IL
V
OH
V
OL
V
OH
IDD
I
OS
C
IN
Conditions
X1/ICLK pin only
X1/ICLK pin only
Min.
4.5
3.5
2
Typ.
2.5
2.5
Max.
5.5
1.5
0.8
Units
V
V
V
V
V
V
V
V
I
OH
= -25 mA
I
OL
= 25 mA
I
OH
= -8 mA
No load, Note 1
Each output
2.4
0.4
VDD-0.4
65
±100
7
0
mA
mA
pF
ppm
Note 1: With ACLK clock at 12.28 MHz.
AC Electrical Characteristics
VDD = 5.0 V ±10%
(unless otherwise noted), Temp 0 to +70° C
Parameter
Input Frequency
Output Clock Rise Time
Output Clock Fall Time
Output Clock Duty Cycle
Absolute Jitter, short term
Skew of 27 MHz Outputs
Symbol
t
OR
t
OF
Conditions
0.8 to 2.0 V
2.0 to 0.8 V
At 1.4 V
Variation from mean
Rising edges at 1.4 V
Min.
Typ.
27
Max. Units
MHz
1.5
1.5
ns
ns
%
ps
500
ps
40
±250
-500
0
60
IDT™
SET-TOP CLOCK SOURCE
4
MK2761A
REV F 051310
MK2761A
SET-TOP CLOCK SOURCE
CLOCK SYNTHESIZER
Thermal Characteristics
Parameter
Thermal Resistance Junction to
Ambient
Symbol
θ
JA
θ
JA
θ
JA
θ
JC
Conditions
Still air
1 m/s air flow
3 m/s air flow
Min.
Typ.
120
115
105
58
Max. Units
°
C/W
°
C/W
°
C/W
°
C/W
Thermal Resistance Junction to Case
Marking Diagram
(MK2761ASLF)
16
9
MK2761ASLF
######
YYWW
1
Notes:
1. ###### is the lot number.
2. YYWW is the last two digits of the year and week that the part was assembled.
3. “LF” denotes Pb (lead) free package.
4. Bottom marking: (origin). Origin = country of origin if not USA.
8
IDT™
SET-TOP CLOCK SOURCE
5
MK2761A
REV F 051310
嵌入式系统
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