512 Kbit / 1 Mbit / 2 Mbit (x8) Many-Time Programmable Flash
GLS27SF512 / GLS27SF010 / GLS27SF020
GLS27SF512 / 010 / 0205.0V-Read 512Kb / 1Mb / 2Mb (x8) MTP flash memories
Data Sheet
FEATURES:
• Organized as 64K x8 / 128K x8 / 256K x8
• 4.5-5.5V Read Operation
• Superior Reliability
– Endurance: At least 1000 Cycles
– Greater than 100 years Data Retention
• Low Power Consumption
– Active Current: 20 mA (typical)
– Standby Current: 10 µA (typical)
• Fast Read Access Time
– 70 ns
• Fast Byte-Program Operation
– Byte-Program Time: 20 µs (typical)
– Chip Program Time:
1.4 seconds (typical) for GLS27SF512
2.8 seconds (typical) for GLS27SF010
5.6 seconds (typical) for GLS27SF020
• Electrical Erase Using Programmer
– Does not require UV source
– Chip-Erase Time: 100 ms (typical)
• TTL I/O Compatibility
• JEDEC Standard Byte-wide EPROM Pinouts
• Packages Available
– 32-lead PLCC
– 32-lead TSOP (8mm x 14mm)
– 32-pin PDIP for GLS27SF010/020
• All non-Pb (lead-free) devices are RoHS compliant
PRODUCT DESCRIPTION
The GLS27SF512/010/020 are a 64K x8 / 128K x8 / 256K
x8 CMOS, Many-Time Programmable (MTP) low cost
flash, manufactured with high performance SuperFlash
technology. The split-gate cell design and thick oxide tun-
neling injector attain better reliability and manufacturability
compared with alternate approaches. These MTP devices
can be electrically erased and programmed at least 1000
times using an external programmer with a 12V power sup-
ply. They have to be erased prior to programming. These
devices conform to JEDEC standard pinouts for byte-wide
memories.
Featuring
high-performance
Byte-Program,
the
GLS27SF512/010/020 provide a Byte-Program time of 20
µs. Designed, manufactured, and tested for a wide spec-
trum of applications, these devices are offered with an
endurance of at least 1000 cycles. Data retention is rated at
greater than 100 years.
The GLS27SF512/010/020 are suited for applications that
require infrequent writes and low power nonvolatile stor-
age. These devices will improve flexibility, efficiency, and
performance while matching the low cost in nonvolatile
applications that currently use UV-EPROMs, OTPs, and
mask ROMs.
To meet surface mount and conventional through hole
requirements, the GLS27SF512 are offered in 32-lead
PLCC, 32-lead TSOP, and 28-pin PDIP packages. The
GLS27SF010/020 are offered in 32-pin PDIP, 32-lead
PLCC, and 32-lead TSOP packages. See Figures 3, 4,
and 5 for pin assignments.
Device Operation
The GLS27SF512/010/020 are a low cost flash solution
that can be used to replace existing UV-EPROM, OTP,
and mask ROM sockets. These devices are functionally
(read and program) and pin compatible with industry
standard EPROM products. In addition to EPROM func-
tionality, these devices also support electrical Erase
operation via an external programmer. They do not
require a UV source to erase, and therefore the pack-
ages do not have a window.
Read
The Read operation of the GLS27SF512/010/020 is con-
trolled by CE# and OE#. Both CE# and OE# have to be
low for the system to obtain data from the outputs. Once
the address is stable, the address access time is equal to
the delay from CE# to output (T
CE
). Data is available at the
output after a delay of T
OE
from the falling edge of OE#,
assuming that CE# pin has been low and the addresses
©2010 Greenliant Systems, Ltd.
www.greenliant.com
S71152-13-000
05/10
512 Kbit / 1 Mbit / 2 Mbit Many-Time Programmable Flash
GLS27SF512 / GLS27SF010 / GLS27SF020
Data Sheet
have been stable for at least T
CE
-T
OE.
When the CE# pin is
high, the chip is deselected and a typical standby current of
10 µA is consumed. OE# is the output control and is used
to gate data from the output pins. The data bus is in high
impedance state when either CE# or OE# is high.
Product Identification Mode
The Product Identification mode identifies the devices as
the GLS27SF512, GLS27SF010 and GLS27SF020 and
manufacturer as Greenliant. This mode may be accessed
by the hardware method. To activate this mode for
GLS27SF010/020, the programming equipment must force
V
H
(11.4-12V) on address A
9
with V
PP
pin at V
DD
(4.5-5.5V)
or V
SS
. To activate this mode for GLS27SF512, the pro-
gramming equipment must force V
H
(11.4-12V) on address
A
9
with OE#/V
PP
pin at V
IL
. Two identifier bytes may then
be sequenced from the device outputs by toggling address
line A
0
. For details, see Tables 3 and 4 for hardware opera-
tion.
TABLE 1: Product Identification
Address
Manufacturer’s ID
Device ID
GLS27SF512
GLS27SF010
GLS27SF020
0001H
0001H
0001H
A4H
A5H
A6H
T1.2 1152
Byte-Program Operation
The GLS27SF512/010/020 are programmed by using an
external programmer. The programming mode for
GLS27SF010/020 is activated by asserting 11.4-12V on
V
PP
pin, V
DD
= 4.5-5.5V, V
IL
on CE# pin, and
V
IH
on OE#
pin. The programming mode for GLS27SF512 is activated
by asserting 11.4-12V on OE#/V
PP
pin, V
DD
= 4.5-5.5V,
and V
IL
on CE# pin. These devices are programmed byte-
by-byte with the desired data at the desired address using
a single pulse (CE# pin low for GLS27SF512 and PGM#
pin low for GLS27SF010/020) of 20 µs. Using the MTP
programming algorithm, the Byte-Programming process
continues byte-by-byte until the entire chip has been pro-
grammed.
Data
BFH
0000H
Chip-Erase Operation
The only way to change a data from a “0” to “1” is by electri-
cal erase that changes every bit in the device to “1”. Unlike
traditional EPROMs, which use UV light to do the Chip-
Erase, the GLS27SF512/010/020 uses an electrical Chip-
Erase operation. This saves a significant amount of time
(about 30 minutes for each Erase operation). The entire
chip can be erased in a single pulse of 100 ms (CE# pin
low for GLS27SF512 and PGM# pin for GLS27SF010/
020). In order to activate the Erase mode for
GLS27SF010/020, the 11.4-12V is applied to V
PP
and A
9
pins, V
DD
= 4.5-5.5V, V
IL
on CE# pin, and
V
IH
on OE# pin.
In order to activate Erase mode for GLS27SF512, the 11.4-
12V is applied to OE#/V
PP
and A
9
pins, V
DD
= 4.5-5.5V,
and V
IL
on CE# pin. All other address and data pins are
“don’t care”. The falling edge of CE# (PGM# for
GLS27SF010/020) will start the Chip-Erase operation.
Once the chip has been erased, all bytes must be verified
for FFH. Refer to Figures 13 and 14 for the flowcharts.
©2010 Greenliant Systems, Ltd.
2
S71152-13-000
05/10
512 Kbit / 1 Mbit / 2 Mbit Many-Time Programmable Flash
GLS27SF512 / GLS27SF010 / GLS27SF020
Data Sheet
X-Decoder
SuperFlash
Memory
A
15
- A
0
Address Buffer
Y-Decoder
CE#
OE#/VPP
A
9
Control Logic
I/O Buffers
DQ
7
- DQ
0
1152 B2.1
FIGURE 1: Functional Block Diagram - GLS27SF512
X-Decoder
SuperFlash
Memory
A
MS
- A
0
Address Buffer
Y-Decoder
CE#
OE#
A
9
V
PP
PGM#
A
MS
= A
17
for GLS27SF020, A
16
for GLS27SF010
I/O Buffers
Control Logic
DQ
7
- DQ
0
1152 B3.2
FIGURE 2: Functional Block Diagram - GLS27SF010/020
©2010 Greenliant Systems, Ltd.
3
S71152-13-000
05/10
512 Kbit / 1 Mbit / 2 Mbit Many-Time Programmable Flash
GLS27SF512 / GLS27SF010 / GLS27SF020
Data Sheet
PGM#
PGM#
A14
VDD
VPP
A12
A15
A16
GLS27SF020
VDD
A12
A15
GLS27SF512
GLS27SF010/020
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
GLS27SF512
A6
A5
A4
A3
A2
A1
A0
NC
DQ0
5
6
7
8
9
10
11
12
13
A13
GLS27SF512
NC
A7
NC
GLS27SF010
VDD
VPP
A12
A15
A16
A17
GLS27SF010/020
A14
A13
A8
A9
A11
OE#
A10
CE#
DQ7
4
3
2
1
32 31 30
29
28
27
26
25
24
23
22
21
A8
A9
A11
NC
OE#/V
PP
A10
CE#
DQ7
DQ6
32-lead PLCC
Top View
14 15 16 17 18 19 20
VSS
DQ1
DQ2
NC
DQ3
DQ4
DQ5
GLS27SF512
DQ1
DQ2
VSS
DQ3
DQ4
GLS27SF010/020
DQ6
DQ5
1152 32-plc P1.5
c
FIGURE 3: Pin Assignments for 32-lead PLCC
GLS27SF020 GLS27SF010 GLS27SF512
A11
A9
A8
A13
A14
NC
NC
VDD
NC
NC
A15
A12
A7
A6
A5
A4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
GLS27SF512 GLS27SF010
OE#/V
PP
A10
CE#
DQ7
DQ6
DQ5
DQ4
DQ3
VSS
DQ2
DQ1
DQ0
A0
A1
A2
A3
OE#
GLS27SF020
OE#
A17
PGM#
VPP
A16
NC
PGM#
VPP
A16
Standard Pinout
Top View
Die Up
1152 32-tsop P2.3
FIGURE 4: Pin Assignments for 32-lead TSOP (8mm x 14mm)
©2010 Greenliant Systems, Ltd.
4
S71152-13-000
05/10
512 Kbit / 1 Mbit / 2 Mbit Many-Time Programmable Flash
GLS27SF512 / GLS27SF010 / GLS27SF020
Data Sheet
GLS27SF020 GLS27SF010
GLS27SF512
A15
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
GLS27SF512
VDD
A14
A13
A8
A9
A11
OE#/VPP
A10
CE#
DQ7
DQ6
DQ5
DQ4
DQ3
1152 28-pdip P3.2
1152 32-pdip P4.2
GLS27SF010 GLS27SF020
1
2
3
4
5
32-pin
6
PDIP
7
8
Top View
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
VDD
PGM#
NC
A14
A13
A8
A9
A11
OE#
A10
CE#
DQ7
DQ6
DQ5
DQ4
DQ3
VDD
PGM#
A17
A14
A13
A8
A9
A11
OE#
A10
CE#
DQ7
DQ6
DQ5
DQ4
DQ3
28-pin
PDIP
T View
op
VPP
A16
A15
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
VSS
VPP
A16
A15
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
VSS
FIGURE 5: Pin Assignments for 28-pin and 32-pin PDIP
TABLE 2: Pin Description
Symbol
A
MS1
-A
0
DQ
7
-DQ
0
CE#
OE#
OE#/V
PP
V
PP
V
DD
V
SS
NC
Pin Name
Address Inputs
Data Input/output
Chip Enable
Output Enable
Output Enable/V
PP
Power Supply for
Program or Erase
Power Supply
Ground
No Connection
Unconnected pins.
T2.4 1152
Functions
To provide memory addresses
To output data during Read cycles and receive input data during Program cycles
The outputs are in tri-state when OE# or CE# is high.
To activate the device when CE# is low
For GLS27SF010/020, to gate the data output buffers during Read operation
For GLS27SF512, to gate the data output buffers during Read operation and high voltage
pin during Chip-Erase and programming operation
For GLS27SF010/020, high voltage pin during Chip-Erase and programming operation
11.4-12V
To provide 5.0V supply (4.5-5.5V)
1. A
MS
= Most significant address
A
MS
= A
15
for GLS27SF512, A
16
for GLS27SF010, and A
17
for GLS27SF020
©2010 Greenliant Systems, Ltd.
5
S71152-13-000
05/10
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