MAX153C ...................................................................0 to +70°C
MAX153E
........................................................... -40°C to +85°C
Storage Temperature Range
............................ -65°C to +150°C
Lead Temperature (soldering, 10s)
................................. +300°C
Soldering Temperature (reflow)
.......................................+260°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these
or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Electrical Characteristics
(V
DD
= +5V ±5%, V
GND
= 0V; Unipolar Input Range: V
SS
= GND, V
REF+
= 5V, V
REF-
= GND; Bipolar Input Range: V
SS
= -5V ±5%,
V
REF+
= 2.5V, V
REF-
= -2.5V; 100% production tested, specifications are given for RD Mode (MODE = GND), T
A
= T
MIN
to T
MAX
,
unless otherwise noted.)
PARAMETER
ACCURACY
Resolution
Total Unadjusted Error
Differential Nonlinearity
Zero-Code Error
Full-Scale Error
DYNAMIC SPECIFICATIONS (Note 1)
Signal-to-Noise Plus Distortion
Noise
Total Harmonic Distortion
Peak Harmonic or Spurious
Noise
Conversion Time (WR-RD Mode)
(Note 2)
Conversion Time (RD Mode)
Full-Power Bandwidth
Input Slew Rate
ANALOG INPUT
Input Voltage Range
Input Leakage Current
Input Capacitance
REFERENCE INPUT
Reference Resistance
V
REF+
Input Voltage Range
V
REF-
Input Voltage Range
R
REF
1
V
REF-
V
SS
2
4
V
DD
V
REF+
kΩ
V
V
V
IN
I
IN
C
IN
-5V ≤ V
IN
≤ +5V
22
V
REF-
V
REF+
±3
V
µA
pF
t
CWR
t
CRD
SINAD
THD
f
SAMPLE
= 1MHz, f
IN
= 195.8kHz
f
SAMPLE
= 1MHz, f
IN
= 195.8kHz
f
SAMPLE
= 1MHz, f
IN
= 195.8kHz
T
A
= +25°C, t
RD
< t
INTL
, C
L
= 20pF
T
A
= +25°C
T
A
= T
MIN
to T
MAX
V
IN
= 5V
P-P
3.14
1
15
45
-50
-50
660
700
875
dB
dB
dB
ns
ns
MHz
V/µs
N
TUE
DNL
Unipolar range
No missing codes guaranteed
Bipolar input range
Bipolar input range
8
±1
±1
±1
±1
Bits
LSB
LSB
LSB
LSB
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
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Maxim Integrated
│
2
MAX153
1Msps, µP-Compatible,
8-Bit ADC with 1µA Power-Down
Electrical Characteristics (continued)
(V
DD
= +5V ±5%, V
GND
= 0V; Unipolar Input Range: V
SS
= GND, V
REF+
= 5V, V
REF-
= GND; Bipolar Input Range: V
SS
= -5V ±5%,
V
REF+
= 2.5V, V
REF-
= -2.5V; 100% production tested, specifications are given for RD Mode (MODE = GND), T
A
= T
MIN
to T
MAX
,
unless otherwise noted.)
PARAMETER
LOGIC INPUTS
Input High Voltage
Input Low Voltage
V
INH
V
INL
CS, WR, RD, PWRDN
MODE
CS, WR, RD, PWRDN
MODE
CS, RD, PWRDN
Input High Current
Input Low Current
Input Capacitance (Note 3)
LOGIC OUTPUTS
Output Low Voltage
Output High Voltage
Floating State Current
Floating Capacitance (Note 3)
POWER REQUIREMENTS
Positive Supply Voltage
Negative Supply Voltage
(Unipolar Operation)
Negative Supply Voltage
(Bipolar Operation)
V
DD
Supply Current
Power-Down VDD Current
V
SS
Supply Current
Power-Down V
SS
Current
Power-Supply Rejection
Note
Note
Note
Note
1:
2:
3:
4:
PSR
I
SS
V
DD
V
SS
V
SS
I
DD
±5% for specified accuracy
V
CS
= V
RD
= 0V,
V
PWRDN
= 5V
MAX153C
MAX153E
±5% for specified accuracy
5
GND
-5
8
8
1
25
12
±1/16
15
20
100
100
100
±1/4
V
V
V
mA
µA
µA
µA
LSB
V
OL
V
OH
I
LKG
C
OUT
I
SINK
= 1.6mA,
INT,
D0–D7
RDY, I
SINK
= 2.6mA
I
SOURCE
= 360µA,
INT,
D0–D7
D0–D7, RDY
D7–D0, RDY
5
4
±3
8
0.4
0.4
V
V
µA
pF
I
INH
I
INL
C
IN
WR
MODE
CS, WR, RD, PWRDN
CS, WR, RD, PWRDN, MODE
5
50
2.4
3.5
0.8
1.5
1
3
200
±1
8
µA
pF
µA
V
V
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
V
CS
= V
RD
= 5V, V
PWRDN
= 0V (Note 4)
V
CS
= V
RD
= 0V, V
PWRDN
= 5V
V
CS
= V
RD
= 5V, V
PWRDN
= 0V
V
DD
= 4.75V to 5.25V, V
REF
+ = 4.75V
(max), unipolar mode
Bipolar input range, V
IN
= ±2.5V
P-P
. WR-RD mode.
See Figure 1 for load circuit. Parameter defined as the time required for the output to cross +0.8V or +2.4V.
Guaranteed by design.
Tested with
CS, RD, PWRDN at CMOS logic levels. Power-down current increases to several hundred) µA at TTL levels.
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Maxim Integrated
│
3
MAX153
1Msps, µP-Compatible,
8-Bit ADC with 1µA Power-Down
TIMING CHARACTERISTICS (Note 5)
(V
DD
= +5V ±5%, V
SS
= 0V for Unipolar Input Range, V
SS
= -5V ±5% for Bipolar Input Range, 100% production tested, T
A
= +25°C,
unless otherwise noted.)
PARAMETER
CS
TO
RD/WR Setup Time
CS
to
RD/WR Hold Time
CS
to
RDY Delay (Note 6)
SYMBOL
t
CSS
t
CSH
t
RDY
C
L
= 50pF
T
A
= T
MIN
to T
MAX
, C
L
= 50pF
C
L
= 20pF
Data-Access Time (RD Mode)
(Note 2)
t
ACC0
T
A
= T
MIN
to T
MAX
, C
L
= 20pF
C
L
= 100pF
T
A
= T
MIN
to T
MAX
, C
L
= 100pF
RD
to
INT Delay (RD Mode)
Data-Hold Time (Note 7)
Delay Time Between
Conversions (Acquisition Time)
Write Pulse Width
Delay Time Between WR
and
RD
Pulses
RD Pulse Width (WR-RD
Mode)
Determined by t
ACC1
Data-Access Time
(WR-RD Mode (Note 2)
t
RD
< t
INL
t
INTH
t
DH
t
P
t
WR
t
RD
t
READ1
C
L
= 50pF
T
A
= T
MIN
to T
MAX
, C
L
= 50pF
T
A
= T
MIN
to T
MAX
160
T
A
= T
MIN
to T
MAX
T
A
= T
MIN
to T
MAX
T
A
= T
MIN
to T
MAX
Figure 6
T
A
= T
MIN
to T
MAX
, Figure 6
C
L
= 20pF, Figure 6
t
ACC1
T
A
= T
MIN
to T
MAX
, C
L
= 20pF, Figure 6
C
L
= 100pF, Figure 6
T
A
= T
MIN
to T
MAX
, C
L
= 100pF, Figure 6
t
RI
t
INTL
t
READ2
T
A
= T
MIN
to T
MAX
C
L
= 50pF
T
A
= T
MIN
to T
MAX
, C
L
= 50pF
Figure 5
T
A
= T
MIN
to T
MAX
, Figure 5
C
L
= 20pF, Figure 5
t
ACC2
T
A
= T
MIN
to T
MAX
, C
L
= 20pF, Figure 5
C
L
= 100pF, Figure 5
T
A
= T
MIN
to T
MAX
, C
L
= 100pF, Figure 5
65
75
65
75
90
110
ns
380
185
0.250
0.280
250
350
160
205
160
205
185
235
150
185
500
610
ns
ns
ns
ns
10
10
50
CONDITIONS
MIN
0
0
70
85
t
CRD
+ 25
t
CRD
+ 30
t
CRD
+ 50
t
CRD
+ 65
80
85
60
70
ns
ns
ns
µs
ns
ns
ns
TYP
MAX
UNITS
ns
ns
ns
RD
to
INT
Delay
WR
to
INT
Delay
RD Pulse Width (WR-RD Mode)
Determinted by t
ACC2
t
RD
> t
INTL
Data-Access Time
(WR-RD Mode) (Note 2)
t
RD
> t
INTL
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Maxim Integrated
│
4
MAX153
1Msps, µP-Compatible,
8-Bit ADC with 1µA Power-Down
TIMING CHARACTERISTICS (Note 5) (continued)
(V
DD
= +5V ±5%, V
SS
= 0V for Unipolar Input Range, V
SS
= -5V ±5% for Bipolar Input Range, 100% production tested, T
A
= +25°C,
unless otherwise noted.)
PARAMETER
WR
to
INT
Delay
(Pipelined Mode)
SYMBOL
t
IHWR
C
L
= 50pF
T
A
= T
MIN
to T
MAX
, C
L
= 50pF
C
L
= 20pF
Data-Access Time After
INT (Note 2)
t
ID
T
A
= T
MIN
to T
MAX
, C
L
= 20pF
C
L
= 100pF
T
A
= T
MIN
to T
MAX
, C
L
= 100pF
CONDITIONS
MIN
TYP
MAX
80
100
30
35
45
60
ns
UNITS
ns
Note 5:
Input control signals are specified with t
r
= t
t
= 5ns, 10% to 90% of +5V and timed from a 1.6V voltage level.
Note 6:
R
L
= 5.1kΩ pullup resistor.
Note 7:
See Figure 2 for load circuit. Parameter defined as the time required for data lines to change 0.5V.
FPGA/CPLD
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