19-3920; Rev 0; 12/05
MAX12527/MAX12528/MAX12529/
MAX12557/MAX12558/MAX12559 Evaluation Kits
General Description
The MAX12527/MAX12528/MAX12529/MAX12557/
MAX12558/MAX12559 evaluation kits (EV kits) are fully
assembled and tested circuit boards that contain all the
components necessary to evaluate the performance of
this family of 12-bit and 14-bit, dual analog-to-digital
converters (ADCs). These ADCs accept differential
analog input signals. The EV kits generate these signals
from user-provided single-ended input sources. The
digital outputs produced by the ADCs can be easily
sampled with a user-provided high-speed logic analyzer
or data-acquisition system. The EV kits operate from
2.0V and 3.3V power supplies.
Features
o
Low-Voltage and Low-Power Operation
o
On-Board Clock-Shaping Circuitry Option
o
On-Board Output Drivers
o
Fully Assembled and Tested
Evaluate: MAX12527/28/29/57/58/59
Ordering Information
PART
MAX12527EVKIT
MAX12528EVKIT
MAX12529EVKIT
MAX12557EVKIT
MAX12558EVKIT
MAX12559EVKIT
TEMP RANGE*
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
IC PACKAGE
68 TQFN-EP**
68 TQFN-EP**
68 TQFN-EP**
68 TQFN-EP**
68 TQFN-EP**
68 TQFN-EP**
Part Selection Table
PART
MAX12559ETK
MAX12558ETK
MAX12557ETK
MAX12529ETK
MAX12528ETK
MAX12527ETK
SAMPLING RATE
(Msps)
96
80
65
96
80
65
RESOLUTION
(Bits)
14
14
14
12
12
12
*EV
kit PC board temperature range only.
**EP
= Exposed paddle.
Component List
DESIGNATION
C1–C4
C5, C6, C11,
C13, C14, C16,
C17, C28–C32,
C45, C46,
C57–C60,
C62–C65
C7–C10
QTY
0
DESCRIPTION
Not installed (0603)
DESIGNATION
C33–C38,
C47, C53
QTY
8
DESCRIPTION
220µF ±20%, 6.3V tantalum
capacitors (C case)
AVX TPSC227M006R0250
10µF ±20%, 6.3V X5R ceramic
capacitors (0805)
TDK C2012X5R0J106M
1.0µF ±20%, 10V X5R ceramic
capacitors (0603)
TDK C1608X5R1A105M
0.01µF ±5%, 25V C0G ceramic
capacitors (0603)
TDK C1608C0G1E103J
1.0µF ±20%, 6.3V X5R ceramic
capacitor (0402)
TDK C1005X5R0J105M
22
0.1µF ±20%, 10V X5R ceramic
capacitors (0402)
TDK C1005X5R1A104M
C39, C40, C41,
C55, C61, C66
6
4
5.6pF ±0.5pF, 50V C0G ceramic
capacitors (0402)
TDK C1005C0G1H5R6D
4.7µF ±20%, 6.3V X5R ceramic
capacitors (0603)
TDK C1608X5R0J475M
0.1µF ±20%, 6.3V X5R ceramic
capacitors (0201)
TDK C0603X5R0J104M
C42, C43,
C44, C56
4
C12,
C21–C27
8
C51, C52
2
C15, C18
C19, C20
4
C67
1
________________________________________________________________
Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
MAX12527/MAX12528/MAX12529/
MAX12557/MAX12558/MAX12559 Evaluation Kits
Evaluate: MAX12527/28/29/57/58/59
Component List (continued)
DESIGNATION
QTY
DESCRIPTION
Dual Schottky diode (SOT23)
Central Semiconductor
CMPD6263S
Vishay BAS70-04
Diodes Inc. BAS70-04
SMA PC mount connectors
2-pin headers
Dual-row, 40-pin headers (2 x 20)
3-pin headers
EMI filters
Murata NFM41PC204F1H3B
U2, U3
2
DESIGNATION
RA1–RA8
T1–T4
T5
TP1–TP6
U1
QTY
8
4
1
6
1
DESCRIPTION
220Ω ±5% resistor arrays
Panasonic EXB-2HV-221J
1:1 RF transformers
Mini-Circuits ADT1-1WT
1:2 RF transformer
Coilcraft TTWB-2-B
Test points
See the
EV Kit Specific
Component List
Low-voltage 16-bit registers
(48-pin TSSOP)
Pericom PI74ALVTC16374 or Texas
Instruments SN74AVC16374DGGR
TinyLogic ULP-A buffer (SC70-5)
Fairchild NC7SV125P5
TinyLogic ULP-A inverter (SC70-6)
Fairchild NC7WV04P6
Shunts
MAX12527/MAX12528/MAX12529/
MAX12557/MAX12558/MAX12559
PC board
D1
1
J1, J2, J7
J3, J4, J8
J5, J6
JU1–JU6
L1–L4
R1–R8,
R13–R16,
R21–R32,
R37, R40–R45
R9–R12
R17–R20
R33–R36
R38, R39
R46, R47
R48
R49–R52
3
3
2
6
4
0
4
4
0
2
2
1
4
Not installed (0603)
75Ω ±0.5% resistors (0603)
110Ω ±0.5% resistors (0603)
Not installed (0402)
49.9Ω ±1% resistors (0603)
100Ω ±1% resistors (0603)
10kΩ potentiometer
24.9Ω ±0.5% resistors (0402)
None
1
U5
None
1
6
U4
1
EV Kit Specific Component List
EV KIT PART NUMBER
MAX12527EVKIT
MAX12528EVKIT
MAX12529EVKIT
MAX12557EVKIT
MAX12558EVKIT
MAX12559EVKIT
U1
REFERENCE
DESIGNATOR
DESCRIPTION
Maxim MAX12527ETK (68-pin thin QFN, 10mm x 10mm x 0.8mm)
Maxim MAX12528ETK (68-pin thin QFN, 10mm x 10mm x 0.8mm)
Maxim MAX12529ETK (68-pin thin QFN, 10mm x 10mm x 0.8mm)
Maxim MAX12557ETK (68-pin thin QFN, 10mm x 10mm x 0.8mm)
Maxim MAX12558ETK (68-pin thin QFN, 10mm x 10mm x 0.8mm)
Maxim MAX12559ETK (68-pin thin QFN, 10mm x 10mm x 0.8mm)
2
_______________________________________________________________________________________
MAX12527/MAX12528/MAX12529/
MAX12557/MAX12558/MAX12559 Evaluation Kits
Component Suppliers
SUPPLIER
AVX
Central Semiconductor
Coilcraft
Diodes Inc.
Fairchild
Murata
Panasonic
Pericom
TDK
Texas Instruments
PHONE
843-946-0238
631-435-1110
847-639-6400
805-446-4800
888-522-5372
770-436-1300
714-373-7366
800-435-2336
847-803-6100
972-644-5580
FAX
843-626-3123
631-435-1824
847-639-1469
805-446-4850
—
770-436-3030
714-737-7323
408-435-1100
847-390-4405
214-480-7800
WEBSITE
www.avxcorp.com
www.centralsemi.com
www.coilcraft.com
www.diodes.com
www.fairchildsemi.com
www.murata.com
www.panasonic.com
www.pericom.com
www.component.tdk.com
www.ti.com
Evaluate: MAX12527/28/29/57/58/59
Note:
Indicate that you are using the MAX12527, MAX12528, MAX12529, MAX12557, MAX12558, and MAX12559 when contacting
these component suppliers.
Quick Start
Recommended Equipment
•
DC power supplies:
Analog (VDD)
Digital (OVDD)
Buffers (VLOGIC)
•
•
•
•
3.3V, 500mA
2.0V, 50mA
2.0V, 100mA
2) Connect the clock signal generator to the input of
the clock bandpass filter.
3) Connect the output of the clock bandpass filter to
the SMA connector labeled J7.
4) Connect the analog input signal generators to the
inputs of the desired analog bandpass filters. For best
results, connect the bandpass filter directly to the SMA
connector and forego any cables in between.
5) Connect the output of the analog bandpass filters to
the SMA connectors labeled J1 and J2. The analog
input signals can be monitored at J3 and J4.
Eliminate cables between bandpass filter outputs
and SMA connectors. If cables must be used, they
should be as short as possible. Add a 3dB to 6dB
attenuator between bandpass filter and SMA con-
nectors to control undesired distortion components
induced by the signal generator.
6) Connect the logic analyzer to headers J5 and J6 to
collect digitized data from channels A and B. See
the
Output Bit Locations
section in this document
for header connections.
7) Connect a 3.3V, 500mA power supply to VDD and
connect its ground terminal to the GND pad.
8) Connect a 2.0V, 50mA power supply to OVDD and
connect its ground terminal to the GND pad.
9) Connect a 2.0V, 100mA power supply to VLOGIC
and connect its ground terminal to the GND pad.
10) Short the VCLK pad to the corresponding GND
pad.
Note:
The VCLK supply is only required when
the data converter is operating in single-ended
clock mode. See the
Configuring the EV Kit for
Single-Ended Clock Operation
section in this docu-
ment for further details.
3
Signal generator with low phase noise and low
jitter for clock input signal (e.g., HP/Agilent 8644B)
Two signal generators with low phase noise for
analog signal inputs (e.g., HP/Agilent 8644B)
Logic analyzer or data-acquisition system (e.g.,
HP/Agilent 16500C)
Narrow-band analog bandpass filters (e.g., Allen
Avionics, K&L Microwave) for input signals and
clock signal
Digital multimeter
•
Procedure
The EV kit is a fully assembled and tested printed cir-
cuit (PC) board. Follow the steps below to verify board
operation.
Do not turn on power supplies or enable
signal generators until all connections are completed.
1) Verify that shunts are installed in the following locations:
JU1 (2-3)
→
Independent reference mode
JU2 (2-3)
→
ADC active (not in power-down mode)
JU3 (2-3)
→
Outputs in two’s-complement format
JU4 (1-2)
→
Differential clock input
JU5 (2-3)
→
No clock division
JU6 (2-3)
→
No clock division
_______________________________________________________________________________________
MAX12527/MAX12528/MAX12529/
MAX12557/MAX12558/MAX12559 Evaluation Kits
Evaluate: MAX12527/28/29/57/58/59
11) Turn on all the power supplies.
12) Enable the signal generators.
13) Set the clock signal generator to the desired clock
frequency. See the
Part Selection Table
for the
appropriate frequency settings for each EV kit. The
amplitude of the generator should be sufficient to
produce a 16dBm signal at the SMA input of the EV
kit. Insertion losses due to the series-connected fil-
ter (step 2) and the interconnecting cables
decrease the amount of power seen at the EV kit
input. Account for these losses when setting the
signal generator amplitude.
14) Set the analog input signal generators to output the
desired test frequency. The amplitude of the gener-
ator should produce a signal that is no larger than
7.5dBm as measured at the SMA input of the EV kit.
Insertion losses due to the series-connected filter
(step 5) and the interconnecting cables decrease
the amount of power seen at the EV kit input.
Account for these losses when setting the signal
generator amplitude. Also account for the attenua-
tion from the 3dB to 6dB attenuator.
15) All signal generators should be phase-locked to
each other.
16) Enable the logic analyzer.
17) Collect data using the logic analyzer.
Power Supplies
For best performance, the EV kits require separate analog,
digital, clock, and buffer power-supply sources. Individual
3.3V and 2.0V power supplies are recommended to
power the analog (VDD) and digital (OVDD) portions of
the converter. A separate 2.0V power supply (VLOGIC) is
used to power the output buffers (U2, U3) of the EV kit.
The on-board clock circuitry (VCLK) is powered by a 3.3V
power supply. The VCLK supply is only required when the
ADC is operating in single-ended clock mode. See the
Configuring the EV Kit for Single-Ended Clock Operation
section for further details.
Converter Power-Down
The MAX12527, MAX12528, MAX12529, MAX12557,
MAX12558, and MAX12559 each feature an active-high
global device power-down pin. Jumper JU2 controls
this feature. See Table 1 for shunt positions.
Table 1. Power-Down Shunt Settings (JU2)
SHUNT
POSITION
1-2
2-3*
PD PIN
OVDD
GND
DESCRIPTION
ADC powered down
ADC active (normal operation)
*Default
configuration: JU2 (2-3).
Clock
Additionally, the data converter allows for either differ-
ential or single-ended signals to drive the clock inputs.
The MAX12527/MAX12528/MAX12529/MAX12557/
MAX12558/MAX12559 EV kits support both methods.
In single-ended operation, the clock signal is applied to
the ADC through a buffer (U5). In differential mode, an
on-board transformer converts a user-provided single-
ended analog input and generates a differential analog
signal, which is then applied to the ADC’s input pins.
Jumper JU4 controls the ADC clock input. See Table 2
for jumper configuration.
Detailed Description
The EV kit is a fully assembled and tested circuit board
that contains all the components necessary to evaluate
the performance of the MAX12527, MAX12528,
MAX12529, MAX12557, MAX12558, or MAX12559.
The ADCs accept differential input signals; however, on-
board transformers (T1–T4) convert a readily available sin-
gle-ended source output to the required differential signal.
The input signals of the ADC can be measured using a
differential oscilloscope probe at headers J3 and J4.
Output drivers (U2 and U3) buffer the output signals of
the data converter. The digital outputs of the EV kit are
accessible at headers J5 and J6.
The EV kits are designed as a four-layer PC board to
optimize the performance of this family of ADCs.
Separate analog, digital, clock, and buffer power
planes minimize noise coupling between analog and
digital signals. 100Ω differential microstrip transmission
lines are used for analog and clock inputs. 50Ω
microstrip transmission lines are used for all digital out-
puts. The trace lengths of the 100Ω differential input
lines are matched to within a few thousandths of an
inch to minimize layout-dependent input-signal skew.
4
Table 2. Clock Selection Shunt Settings (JU4)
SHUNT
POSITION
1-2*
DIFFCLK/
SECLK
PIN
OVDD
DESCRIPTION
Differential clock mode.
Single-ended clock mode.
See the
Configuring the EV Kit for
Single-Ended Clock Operation
section
for further details.
2-3
GND
*Default
configuration: JU4 (1-2).
_______________________________________________________________________________________
MAX12527/MAX12528/MAX12529/
MAX12557/MAX12558/MAX12559 Evaluation Kits
Configuring the EV Kits for
Single-Ended Clock Operation
To configure the MAX12527/MAX12528/MAX12529/
MAX12557/MAX12558/MAX12559 EV kits for single-
ended clock operation, the following modifications must
be made to the clock circuit:
1) Cut the trace at locations R41, R43, and R44.
2) Install 0Ω resistors at locations R40, R42, and R45.
3) Install a 49.9Ω ±1% resistor at location R37.
4) Connect a 3.3V power supply to VCLK (needs to be
capable of sourcing up to 10mA output current).
Connect the ground terminal of this supply to GND.
In single-ended clock configuration, potentiometer R48
can be utilized to control the duty cycle of the clock
input signal. Measure the clock input at J8 and adjust
R48 until the desired duty cycle is achieved.
Clock-Divider Control
The MAX12527, MAX12528, MAX12529, MAX12557,
MAX12558, and MAX12559 each feature internal
divide-by-2/divide-by-4 clock-divider circuitry (DIV2,
DIV4). Jumpers JU5 and JU6 control this circuitry.
Refer to the individual ADC data sheets for a detailed
explanation of the internal clock divider. See Table 3 for
jumper configuration.
Optimizing the Analog Input Network for
Different Input Frequencies
The EV kits are designed for excellent AC performance
across a broad 3MHz to 400MHz input frequency range.
The design can be further optimized by adjusting compo-
nents C7–C10 and R49–R52. See Table 4 for the appropri-
ate component values for specific input frequency ranges.
Evaluate: MAX12527/28/29/57/58/59
Table 4. Component Selection for
Optimized AC Performance
INPUT
FREQUENCY
RANGE (MHz)
3 to 400*
< 10
10 to 125
> 125
C7–C10
COMPONENT
VALUES (pF)
5.6
12 to 22
12
5.6 to 12
R49–R52
COMPONENT
VALUES (Ω)
25
0
25 to 50
0
*Default
EV kit configuration.
Reference
The MAX12527, MAX12528, MAX12529, MAX12557,
MAX12558, and MAX12559 feature numerous refer-
ence operation modes. The default EV kit configuration
connects the ADC’s internal 2.048V reference output to
the reference input. In this case, the converter gener-
ates the REFN, REFP, and COM voltages from this
input (refer to the individual ADC’s data sheet for a
more detailed explanation).
To apply a user-supplied reference, cut the trace at
location R33 and connect the desired external refer-
ence to the REFIN pad. Alternatively, the EV kit can be
configured to use a divided internal reference value. If
the desired reference voltage is less than 2.048V, cut
the trace at location R33 and install resistors in loca-
tions R33 and R34. Calculate the resistor values from
the equations below:
R34
=
V
REF
V
REFOUT
×
R
T
Table 3. Clock-Divider Shunt Settings
(JU5, JU6)
SHUNT
POSITION
JU5
2-3*
1-2
2-3
1-2
JU6
2-3*
2-3
1-2
1-2
PIN
CONNECTION
DIV2
GND
OVDD
GND
OVDD
DIV4
GND
GND
Normal clock mode
Divide-by-2 clock mode (DIV2)
DESCRIPTION
OVDD Divide-by-4 clock mode (DIV4)
OVDD
INVALID
*Default
configuration: JU5 (2-3), JU6 (2-3).
Input Signal
Although this family of ADCs accepts differential analog
input signals, the EV kit only requires single-ended ana-
log input signals, with amplitudes less than 7.5dBm.
Insertion losses due to a series-connected filter and the
interconnecting cables decrease the amount of power
seen at the EV kit input. Account for these losses when
setting the signal generator amplitude. On-board trans-
formers (T1–T4) convert the single-ended analog input
signals and generate the recommended differential
analog signals at the ADCs’ differential input pins.
R33 = R
T
- R34
where:
V
REF
= desired reference voltage
V
REFOUT
= ADC’s internal reference voltage of 2.048V
R
T
= ADC’s minimum reference resistance
≈
10kΩ
_______________________________________________________________________________________
5
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