S i 3 2 1 0 / S i 3 2 11
P
RO
SLIC
®
P
ROGRAMMABLE
CMOS SLIC/C
ODEC
W I T H
R
INGING
/ B
A TT E R Y
V
OLTA GE
G
ENERATION
Features
100% programmable global solution
Performs all BORSCHT functions
DC-DC controller provides tracking
battery from a 3.3–35V input (Si3210)
Minimizes power in all modes
Dynamic 0 to –94.5 V output
Choice of inductor (low cost) or
transformer (high efficiency)
Programmable line-feed parameters
2-wire AC impedance and hybrid
Constant current feed (20 to 41 mA)
Loop closure and ring trip thresholds
and filtering
Internal balanced ringing up to 90V
PK
5 REN up to 4 kft; 3 REN up to 8 kft
Programmable frequency, amplitude,
cadence, and wave shape
Fixed Wireless (cellular) Terminals
Terminal Adapters
PBX/IP-PBX/Key telephone systems
Voice-over-IP Systems:
DSL/EMTAs/FTTx
WiMax/LTE
Description
The Si3210/11
chipset provides a complete analog telephone interface ideal
for customer premise equipment (CPE). It integrates a subscriber line interface circuit
(SLIC), voice codec, and battery generation (Si3210) or battery selection (Si3211) into
a single CMOS integrated circuit. The battery supply continuously adapts its output
voltage to minimize power dissipation and enables the entire circuit to be powered
from a single 3.3 or 5 V supply (Si3210). The CMOS ProSLIC interfaces to the line
through either the Si3201 Line-feed IC or a discrete line-feed circuit.
Si3210/11 features include software-configurable 5 REN internal ringing up to 90 VPK,
DTMF generation and decoding, Caller ID generation, and a comprehensive set of
telephony signaling capabilities for global operation with a single hardware solution.
The Si3210/11 is packaged in a 38-pin QFN or TSSOP, and the Si3201 is packaged in
a thermally-enhanced 16-pin SOIC.
ProSLIC
®
DTX
FSYNC
RESET
SDCH/DIO1
SDCL/DIO2
V
DDA1
IREF
CAPP
QGND
CAPM
STIPDC
SRINGDC
1 38 37 36 35 34 33 32 31
30
2
3
4
5
6
7
8
9
29
28
27
26
25
24
23
22
21
DRX
PCLK
INT
CS
SCLK
SDI
SDO
SDITHRU
DCDRV/DCSW
DCFF/DOUT
TEST
GNDD
VDDD
ITIPN
ITIPP
V
DDA2
IRINGP
IRINGN
IGMP
Applications
Functional Block Diagram
INT
CS
SCLK
SDO
SDI
DTX
Control
Interface
Compression
DTMF
Decode
Gain/
Attenuation/
Filter
Tone
Generators
Gain/
Attenuation/
Filter
D/A
A/D
Line
Feed
Control
TIP
Prog.
Hybrid
Linefeed
Interface
RING
Z
S
RESET
FSYNC
PCLK
PLL
Expansion
Rev. 1.61 1/12
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10
11
Programmable audio processing
DTMF encoding and decoding
12 kHz/16 kHz pulse metering
Phase-continuous FSK (caller ID)
Dual tone generators
-Law/A-Law
and linear PCM audio
Extensive test and diagnostic features
Multiple loopback test modes
DC line V/I measurements
Supports GR-909 MLT
Comprehensive design tools
Reference schematic and PCB
layout
ProSLIC API
abstracts SLIC
functions, minimizing software
development
RoHS-compliant packages
SPI and PCM bus digital interfaces
Ordering Information
See page 130.
QFN Pin Assignments
Si3210/11
QFN
12 13 14 15 16 17 18 19 20
U.S. Patent #6,567,521
U.S. Patent #6,812,744
Si3210/11
Line
Status
DRX
PCM
Interface
DC-DC Converter Controller
(Si3210 only)
Discrete
Components
Copyright © 2012 by Silicon Laboratories
STIPE
SVBAT
SRINGE
STIPAC
SRINGAC
IGMN
GNDA
Si3210
Si3210/Si3211
T
ABLE
OF
C
ONTENTS
1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
2. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
2.1. Linefeed Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
2.2. Battery Voltage Generation and Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
2.3. Tone Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
2.4. Ringing Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
2.5. Pulse Metering Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
2.6. DTMF Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
2.7. Audio Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
2.8. Two-Wire Impedance Matching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
2.9. Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
2.10. Interrupt Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
2.11. Serial Peripheral Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
2.12. PCM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
2.13. Companding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
3. Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
4. Indirect Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .118
4.1. DTMF Decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .118
4.2. Oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
4.3. Digital Programmable Gain/Attenuation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
4.4. SLIC Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
4.5. FSK Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .125
5. Pin Descriptions: Si3210/11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
6. Pin Descriptions: Si3201 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
7. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
8. Package Outlines and PCB Land Patterns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
8.1. 38-Pin QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .132
8.2. 38-Pin TSSOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
8.3. 16-Pin ESOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
9. Product Identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .140
9.1. Ordering Part Number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
9.2. Marking Part Number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
10. Package Marking (Top Mark) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
10.1. QFN Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
10.2. TSSOP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
10.3. SOIC (Si3201) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .143
Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .148
2
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Rev. 1.61
Si3210/Si3211
1. Electrical Specifications
Table 1. Absolute Maximum Ratings and Thermal Information
1
Parameter
DC Supply Voltage
Input Current, Digital Input Pins
Digital Input Voltage
Operating Temperature Range
2
Storage Temperature Range
Symbol
Si3210/11
V
DDD
, V
DDA1
, V
DDA2
I
IN
V
IND
T
A
–0.5 to 6.0
±10
–0.3 to (V
DDD
+ 0.3)
–40 to 100
–40 to 150
70
35
V
mA
V
C
C
C/W
C/W
W
V
V
V
V
C
C
C/W
W
Value
Unit
TSSOP-38 Thermal Resistance, Typical
QFN-38 Thermal Resistance, Typical
Continuous Power Dissipation
2
DC Supply Voltage
Battery Supply Voltage
Input Voltage: TIP, RING, SRINGE, STIPE pins
Operating Temperature Range
2
Storage Temperature Range
Input Voltage: ITIPP, ITIPN, IRINGP, IRINGN pins
SOIC-16 Thermal Resistance, Typical
3
Continuous Power Dissipation
2
Notes:
1.
Permanent device damage may occur if the absolute maximum ratings are exceeded. Functional operation should be
restricted to the conditions as specified in the operational sections of this data sheet. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
2.
Operation above 125 °C junction temperature may degrade device reliability.
3.
Thermal resistance assumes a multi-layer PCB with the exposed pad soldered to a topside PCB pad.
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T
STG
JA
JA
P
D
0.7
Si3201
V
DD
–0.5 to 6.0
–104
V
BAT
V
IN
T
A
V
INHV
–40 to 100
–40 to 150
55
T
STG
JA
P
D
Rev. 1.61
(V
BAT
– 0.3) to (V
DD
+ 0.3)
–0.3 to (V
DD
+ 0.3)
0.8 at 70 °C
0.6 at 85 °C
3
Si3210/Si3211
Table 2. Recommended Operating Conditions
Parameter
Ambient Temperature
Ambient Temperature
Si3210/11 Supply Voltage
Si3201 Supply Voltage
Si3201 Battery Voltage
Symbol
T
A
T
A
V
DDD
,V
DDA1
,
V
DDA2
V
DD
V
BAT
V
BATH
= V
BAT
Test Condition
F-grade
G-grade
Min*
0
–40
3.13
3.13
–96
Typ
25
25
3.3/5.0
3.3/5.0
—
Max*
70
85
5.25
5.25
–10
Unit
°
C
°
C
V
V
V
*Note:
All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions.
Typical values apply at nominal supply voltages and an operating temperature of 25 °C unless otherwise stated.
Product specifications are only guaranteed for the typical application circuit (including component tolerances).
Table 3. AC Characteristics
Parameter
(V
DDA
, V
DDD
= 3.13 to 5.25 V, T
A
= 0 to 70 °C for F-Grade, –40 to 85 °C for G-Grade)
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Test Condition
Min
Typ
TX/RX Performance
THD = 1.5%
2.5
—
—
1
Max
Unit
Overload Level
—
–45
V
PK
dB
Single Frequency Distortion
2-wire – PCM or
PCM – 2-wire:
200 Hz–3.4 kHz
—
Signal-to-(Noise + Distortion) Ratio
2
Audio Tone Generator
Signal-to-Distortion Ratio
2
Intermodulation Distortion
Gain Accuracy
2
200 Hz to 3.4 kHz
D/A or A/D 8-bit
Active off-hook, and OHT,
any ZAC
0 dBm0, Active off-hook,
and OHT, any Zac
2-wire to PCM, 1014 Hz
PCM to 2-wire, 1014 Hz
Figure 1
—
—
45
—
—
—
–45
0.5
0.5
—
—
dB
dB
dB
dB
—
0
0
–0.5
–0.5
Gain Accuracy over Frequency
Group Delay over Frequency
Figure 3,4
—
Figure 5,6
1014 Hz sine wave,
reference level –10 dBm
signal level:
3 to –37 dB
–37 to –50 dB
–50 to –60 dB
–0.25
–0.5
–1.0
—
–0.017
–0.25
–0.1
—
Gain Tracking
3
—
—
—
1100
—
—
—
0.25
0.5
1.0
—
0.017
0.25
0.1
dB
dB
dB
µs
dB
dB
dB
Round-Trip Group Delay
Gain Step Accuracy
Gain Variation with Temperature
Gain Variation with Supply
at 1000 Hz
–6 to +6 dB
All gain settings
V
DDA
= V
DDA
= 3.3/5 V ±5%
4
Rev. 1.61
Si3210/Si3211
Table 3. AC Characteristics (Continued)
(V
DDA
, V
DDD
= 3.13 to 5.25 V, T
A
= 0 to 70 °C for F-Grade, –40 to 85 °C for G-Grade)
Parameter
2-Wire Return Loss
Transhybrid Balance
Test Condition
200 Hz to 3.4 kHz
300 Hz to 3.4 kHz
Noise Performance
C-Message Weighted
Min
30
30
—
—
—
Typ
35
—
—
—
—
Max
—
—
15
–75
18
—
—
—
Unit
dB
dB
dBrnC
dBmP
dBrn
dB
dB
dB
PSRR from VDDA
PSRR from VBAT
PSRR from VDDD
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3 kHz flat
RX and TX, DC to 3.4 kHz
40
—
RX and TX, DC to 3.4 kHz
40
—
RX and TX, DC to 3.4 kHz
40
—
Longitudinal Performance
200 Hz to 3.4 kHz,
Q1,Q2
150, 1% mismatch
Q1,Q2
½
60 to 240
5
Using Si3201
Q1,Q2
½
300 to 800
5
200 Hz to 3.4 kHz
56
60
43
53
60
60
—
53
60
40
200 Hz to 3.4 kHz at TIP or
RING
Register selectable
ETBO/ETBA
Idle Channel Noise
4
Psophometric Weighted
—
—
—
—
—
dB
dB
dB
dB
dB
Longitudinal to Metallic
or PCM Balance
Metallic to Longitudinal Balance
Longitudinal Impedance
00
01
10
—
—
—
33
17
17
—
—
—
Active off-hook
200 Hz to 3.4 kHz
Register selectable
ETBO/ETBA
Longitudinal Current per Pin
00
01
10
—
—
—
4
8
12
—
—
—
mA
mA
mA
Notes:
1.
The input signal level should be 0 dBm0 for frequencies greater than 100 Hz. For 100 Hz and below, the level should
be
–10 dBm0. The output signal magnitude at any other frequency will be smaller than the maximum value specified.
2.
Analog signal measured as V
TIP
– V
RING
. Assumes ideal line impedance matching.
3.
The quantization errors inherent in the µ/A-law companding process can generate slightly worse gain tracking
performance in the signal range of 3 to –37 dB for signal frequencies that are integer divisors of the 8 kHz PCM
sampling rate.
4.
The level of any unwanted tones within the bandwidth of 0 to 4 kHz does not exceed –55 dBm.
5.
Assumes normal distribution of betas.
Rev. 1.61
5
FPGA/CPLD
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