MM74HC125, MM74HC126 — 3-STATE Quad Buffers
February 2008
MM74HC125, MM74HC126
3-STATE Quad Buffers
Features
■
Typical propagation delay: 13ns
■
Wide operating voltage range: 2V–6V
■
Low input current: 1µA maximum
■
Low quiescent current: 80µA maximum (74HC)
■
Fanout of 15 LS-TTL loads
General Description
The MM74HC125 and MM74HC126 are general pur-
pose 3-STATE high speed non-inverting buffers utilizing
advanced silicon-gate CMOS technology. They have
high drive current outputs which enable high speed oper-
ation even when driving large bus capacitances. These
circuits possess the low power dissipation of CMOS
circuitry, yet have speeds comparable to low power
Schottky TTL circuits. Both circuits are capable of driving
up to 15 low power Schottky inputs.
The MM74HC125 require the 3-STATE control input C to
be taken high to put the output into the high impedance
condition, whereas the MM74HC126 require the control
input to be low to put the output into high impedance.
All inputs are protected from damage due to static
discharge by diodes to V
CC
and ground.
Ordering Information
Order Number
MM74HC125M
MM74HC125SJ
MM74HC125MTC
MM74HC125N
MM74HC126M
MM74HC126SJ
MM74HC126MTC
MM74HC126N
Package
Number
M14A
M14D
MTC14
N14A
M14A
M14D
MTC14
N14A
Package Description
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150"
Narrow
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153,
4.4mm Wide
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150"
Narrow
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153,
4.4mm Wide
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.
All packages are lead free per JEDEC: J-STD-020B standard.
©1983 Fairchild Semiconductor Corporation
MM74HC125, MM74HC126 Rev. 1.3.0
www.fairchildsemi.com
MM74HC125, MM74HC126 — 3-STATE Quad Buffers
Connection Diagrams
Pin Assignments for DIP, SOIC, SOP and TSSOP
Top View (MM74HC125)
Top View (MM74HC126)
Truth Tables
Inputs
A
H
L
X
Output
C
L
L
H
Inputs
A
H
L
X
Output
C
H
H
L
Y
H
L
Z
Y
H
L
Z
MM74HC125
MM74HC126
©1983 Fairchild Semiconductor Corporation
MM74HC125, MM74HC126 Rev. 1.3.0
www.fairchildsemi.com
2
MM74HC125, MM74HC126 — 3-STATE Quad Buffers
Absolute Maximum Ratings
(1)
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
Symbol
V
CC
V
IN
V
OUT
I
IK
, I
OK
I
OUT
I
CC
T
STG
P
D
Supply Voltage
DC Input Voltage
DC Output Voltage
Clamp Diode Current
DC Output Current, per pin
Parameter
Rating
–0.5 to +7.0V
–1.5 to V
CC
+1.5V
–0.5 to V
CC
+0.5V
±20mA
35mA
±70mA
–65°C to +150°C
600mW
500mW
260°C
DC V
CC
or GND Current, per pin
Storage Temperature Range
Power Dissipation
Note 2
S.O. Package only
Lead Temperature (Soldering 10 seconds)
T
L
Notes:
1. Unless otherwise specified all voltages are referenced to ground.
2. Power Dissipation temperature derating — plastic “N” package: –12mW/°C from 65°C to 85°C.
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to absolute maximum ratings.
Symbol
V
CC
V
IN
, V
OUT
T
A
t
r
, t
f
Supply Voltage
DC Input or Output Voltage
Parameter
Min.
2
0
–40
Max.
6
V
CC
+85
1000
500
400
Units
V
V
°C
ns
ns
ns
Operating Temperature Range
Input Rise or Fall Times
V
CC
=
2.0V
V
CC
=
4.5V
V
CC
=
6.0V
©1983 Fairchild Semiconductor Corporation
MM74HC125, MM74HC126 Rev. 1.3.0
www.fairchildsemi.com
3
MM74HC125, MM74HC126 — 3-STATE Quad Buffers
DC Electrical Characteristics
(3)
T
A
=
25°C
Symbol
V
IH
T
A
=
–40°C T
A
=
–40°C
to 85°C
to 125°C
Guaranteed Limits
Units
V
1.5
3.15
4.2
0.5
1.35
1.8
1.9
4.4
5.9
3.84
5.34
0.1
0.1
0.1
0.33
0.33
±5
1.5
3.15
4.2
0.5
1.35
1.8
1.9
4.4
5.9
3.7
5.2
0.1
0.1
0.1
0.4
0.4
±10
µA
V
V
V
Parameter
Minimum HIGH
Level Input
Voltage
Maximum LOW
Level Input
Voltage
Minimum HIGH
Level Output
Voltage
Conditions
V
CC
(V) Typ.
2.0
4.5
6.0
2.0
4.5
6.0
1.5
3.15
4.2
0.5
1.35
1.8
2.0
4.5
6.0
4.2
5.7
0
0
0
0.2
0.2
1.9
4.4
5.9
3.98
5.48
0.1
0.1
0.1
0.26
0.26
±0.5
V
IL
V
OH
V
IN
=
V
IH
or V
IL
,
|I
OUT
|
≤
20µA
V
IN
=
V
IH
or V
IL
,
|I
OUT
|
≤
6.0mA
V
IN
=
V
IH
or V
IL
,
|I
OUT
|
≤
7.8mA
2.0
4.5
6.0
4.5
6.0
2.0
4.5
6.0
4.5
6.0
6.0
V
OL
Maximum LOW
Level Output
Voltage
V
IN
=
V
IH
or V
IL
,
|I
OUT
|
≤
20µA
V
IN
=
V
IH
or V
IL
,
|I
OUT
|
≤
6.0mA
V
IN
=
V
IH
or V
IL
,
|I
OUT
|
≤
7.8mA
I
OZ
Maximum
3-STATE Output
Leakage Current
Maximum Input
Current
Maximum
Quiescent
Supply Current
V
IN
=
V
IH
or V
IL
,
V
OUT
=
V
CC
or GND,
C
n
=
Disabled
V
IN
=
V
CC
or GND
V
IN
=
V
CC
or GND,
I
OUT
=
0µA
I
IN
I
CC
6.0
6.0
±0.1
8.0
±1.0
80
±1.0
160
µA
µA
Note:
3. For a power supply of 5V ±10% the worst case output voltages (V
OH
, and V
OL
) occur for HC at 4.5V. Thus the 4.5V
values should be used when designing with this supply. Worst case V
IH
and V
IL
occur at V
CC
=
5.5V and 4.5V
respectively. (The V
IH
value at 5.5V is 3.85V.) The worst case leakage current (I
IN
, I
CC
, and I
OZ
) occur for CMOS at
the higher voltage and so the 6.0V values should be used.
©1983 Fairchild Semiconductor Corporation
MM74HC125, MM74HC126 Rev. 1.3.0
www.fairchildsemi.com
4
MM74HC125, MM74HC126 — 3-STATE Quad Buffers
AC Electrical Characteristics
V
CC
=
5V, T
A
=
25°C, C
L
=
45pF, t
r
=
t
f
=
6ns
Symbol
t
PHL
, t
PLH
t
PZH
t
PHZ
t
PZL
t
PLZ
Parameter
Maximum Propagation Delay Time
Maximum Output Enable Time to HIGH
Level
Maximum Output Disable Time from
HIGH Level
Maximum Output Enable Time to LOW
Level
Maximum Output Disable Time from
LOW Level
Conditions
R
L
=
1kΩ
R
L
=
1kΩ, C
L
=
5pF
R
L
=
1kΩ
R
L
=
1kΩ, C
L
=
5pF
Typ.
13
13
17
18
13
Guaranteed
Limit
18
25
25
25
25
Units
ns
ns
ns
ns
ns
AC Electrical Characteristics
V
CC
=
2.0V to 6.0V, C
L
=
50pF, t
r
=
t
f
=
6ns (unless otherwise specified)
T
A
=
25°C
Symbol
Parameter
V
CC
(V)
2.0
4.5
6.0
t
PLH
, t
PHL
Maximum Propagation
Delay Time
2.0
4.5
6.0
t
PZH
, t
PZL
Maximum Output
Enable Time
2.0
4.5
6.0
t
PHZ
, t
PLZ
Maximum Output
Disable Time
2.0
4.5
6.0
t
PZL
, t
PZH
Maximum Output
Enable Time
2.0
4.5
6.0
t
TLH
, t
THL
Maximum Output
Rise and Fall Time
2.0V
4.5V
6.0V
C
IN
C
OUT
C
PD
Input Capacitance
Output Capacitance
Outputs
Power Dissipation
Capacitance
(per gate)
(4)
Enabled
Disabled
C
L
=
50pF
C
L
=
150pF,
R
L
=
1kΩ
R
L
=
1kΩ
R
L
=
1kΩ
C
L
=
150pF
T
A
=
–40°C
to 85°C
125
25
21
163
33
28
156
31
26
156
31
26
175
35
30
75
15
13
10
20
T
A
=
–40°C
to 125°C
Units
ns
150
30
25
195
39
39
188
38
31
188
38
31
210
42
36
90
18
15
10
20
pF
pF
pF
ns
ns
ns
ns
ns
Conditions Typ.
40
14
12
35
14
12
25
14
12
25
14
12
35
15
13
30
7
6
5
15
45
6
100
20
17
130
26
22
125
25
21
125
25
21
140
28
24
60
12
10
10
20
Guaranteed Limits
t
PHL
, t
PLH
Maximum Propagation
Delay Time
Note:
4. C
PD
determines the no load dynamic power consumption, P
D
=
C
PD
V
CC2
f + I
CC
V
CC
, and the no load dynamic
current consumption, I
S
=
C
PD
V
CC
f + I
CC
.
©1983 Fairchild Semiconductor Corporation
MM74HC125, MM74HC126 Rev. 1.3.0
www.fairchildsemi.com
5
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