19-3464; Rev 1; 10/10
KIT
ATION
EVALU
BLE
AVAILA
12-Bit, 170Msps ADC with CMOS
Outputs for Wideband Applications
General Description
Features
o
170Msps Conversion Rate
o
SNR = 64.3dB, f
IN
= 100MHz at 170Msps
o
SFDR = 73dBc, f
IN
= 100MHz at 170Msps
o
±0.7 LSB INL, ±0.25 DNL (typ)
o
907mW Power Dissipation at 170Msps
o
On-Chip Selectable Divide-by-2 Clock Input
o
Parallel or Demux Parallel Digital CMOS Outputs
o
Reset Option for Synchronizing Multiple ADCs
o
Data Clock Output
o
Offset Binary or Two’s-Complement Output
o
Evaluation Kit Available (MAX19542EVKIT)
MAX19542
The MAX19542 monolithic 12-bit, 170Msps analog-to-
digital converter (ADC) is optimized for outstanding
dynamic performance at high-IF frequencies of
300MHz and beyond. This device operates with con-
version rates up to 170Msps while consuming only
907mW.
At 170Msps and an input frequency of 240MHz, the
MAX19542 achieves a spurious-free dynamic range
(SFDR) of 76.4dBc. The MAX19542 features an excel-
lent signal-to-noise ratio (SNR) of 65dB at 10MHz that
remains flat (within 3dB) for input tones up to 250MHz.
This makes the MAX19542 ideal for wideband applica-
tions such as power-amplifier predistortion in cellular
base-station transceiver systems.
The MAX19542 operates in either parallel mode where
the data outputs appear on a single parallel port at the
sampling rate, or in demux parallel mode, where the out-
puts appear on two separate parallel ports at one-half
the sampling rate. See the
Modes of Operation
section.
The MAX19542 operates on a single 1.8V supply. The
analog input is differential and can be AC- or DC-cou-
pled. The ADC also features a selectable on-chip
divide-by-2 clock circuit that allows clock frequencies
as high as 340MHz. This helps to reduce the phase
noise of the input clock source, allowing for higher
dynamic performance. For best performance, a differ-
ential LVPECL sampling clock is recommended. The
digital outputs are CMOS compatible and the data for-
mat can be selected to be either two’s complement or
offset binary.
A pin-compatible, 12-bit, 125Msps version of the
MAX19542 is also available. Refer to the MAX19541
data sheet for more information.
The MAX19542 is available in a 68-pin QFN with
exposed pad (EP) and is specified over the extended
(-40°C to +85°C) temperature range.
Ordering Information
PART
MAX19542EGK+
TEMP RANGE
-40°C to +85°C
PIN-PACKAGE
68 QFN-EP*
+Denotes
a lead(Pb)-free/RoHS-compliant package.
*EP = Exposed pad.
Pin Configuration
OGND
AGND
AGND
AVCC
OVCC
AVCC
AVCC
TOP VIEW
T/B
ITL
DA11
DA10
ORA
DA9
DA8
DA7
DA6
+
AVCC
AGND
REFIO
REFADJ
AGND
AVCC
AGND
INP
INN
1
2
3
4
5
6
7
8
9
68
67 66 65 64
63 62 61 60 59 58
57 56 55 54 53 52
51
DA4
50
DA3
49
DA2
48
DA1
47
DA0
46
ORB
45
OGND
44
OVCC
Applications
Base-Station Power Amplifier Linearization
Cable Head-End Receivers
Wireless and Wired Broadband Communication
Communications Test Equipment
Radar and Satellite Subsystems
DA5
43
DCLKP
42
DCLKN
41
OVCC
40
DB11
39
DB10
38
DB9
37
DB8
36
DB7
35
DB6
AGND
10
AVCC
11
AVCC
12
AVCC
13
AVCC
14
RESET
15
DEMUX
16
CLKDIV
17
MAX19542
EP
18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
AGND
AVCC
CLKP
AGND
OGND
OVCC
OVCC
DB0
DB1
DB2
AGND
AGND
CLKN
AVCC
DB3
DB4
NOTE:
EXPOSED PAD CONNECTED TO AGND.
QFN
________________________________________________________________
Maxim Integrated Products
DB5
1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
12-Bit, 170Msps ADC with CMOS
Outputs for Wideband Applications
MAX19542
ABSOLUTE MAXIMUM RATINGS
AV
CC
to AGND ......................................................-0.3V to +2.1V
OV
CC
to OGND .....................................................-0.3V to +2.1V
AV
CC
to OV
CC
.......................................................-0.3V to +2.1V
AGND to OGND ....................................................-0.3V to +0.3V
Analog Inputs (INP, INN) to AGND ..........-0.3V to (AV
CC
+ 0.3V)
All Digital Inputs to AGND........................-0.3V to (AV
CC
+ 0.3V)
REFIO, REFADJ to AGND ........................-0.3V to (AV
CC
+ 0.3V)
All Digital Outputs to OGND ....................-0.3V to (OV
CC
+ 0.3V)
Maximum Current into Any Pin ....................................... ±50mA
ESD on All Pins (Human Body Model).............................±2000V
Continuous Power Dissipation (T
A
= +70°C)
68-Pin QFN (derate 41.7mW/°C above +70°C) ........ 3333mW
Operating Temperature Range ..........................-40°C to +85°C
Junction Temperature .....................................................+150°C
Storage Temperature Range ............................-60°C to +150°C
Lead Temperature (soldering, 10s) ................................+300°C
Soldering Temperature (reflow) ......................................+260°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V
AVCC
= V
OVCC
= 1.8V, V
AGND
= V
OGND
= 0V, f
SAMPLE
= 170MHz, DEMUX = 0, differential LVPECL clock input drive, 0.1µF capac-
itor on REFIO, internal reference, T
A
= T
MIN
to T
MAX
, unless otherwise noted. T
A
≥
+25°C guaranteed by production test, T
A
< +25°C
guaranteed by design and characterization. Typical values are at T
A
= +25°C.)
PARAMETER
DC ACCURACY
Resolution
Integral Nonlinearity
Differential Nonlinearity
Transfer Curve Offset
Offset Temperature Drift
ANALOG INPUTS (INP, INN)
Full-Scale Input Voltage Range
Full-Scale Range Temperature
Drift
Common-Mode Input Range
Input Capacitance
Differential Input Resistance
Full-Power Analog Bandwidth
REFERENCE (REFIO, REFADJ)
Reference Output Voltage
Reference Temperature Drift
REFADJ Input High Voltage
SAMPLING CHARACTERISTICS
Maximum Sampling Rate
Minimum Sampling Rate
Clock Duty Cycle
Aperture Delay
Aperture Jitter
t
AD
t
AJ
f
SAMPLE
f
SAMPLE
Set by clock-management circuit
Figure 4
170
20
40 to 60
620
0.2
MHz
MHz
%
ps
ps
RMS
V
REFADJ
Used to disable the internal reference
V
AVCC
- 0.3
V
REFIO
1.22
1.245
90
1.27
V
ppm/°C
V
V
CM
C
IN
R
IN
FPBW
3.00
V
FS
(Note 1)
1300
1410
130
1.365
±0.15
3
4.3
900
6.25
1510
mV
P-P
ppm/°C
V
pF
kΩ
MHz
INL
DNL
V
OS
f
IN
= 10MHz (Note 1)
f
IN
= 10MHz, no missing codes (Note 1)
(Note 1)
12
-2.5
-0.75
-3
40
±0.7
±0.25
+2.5
+0.75
+3
Bits
LSB
LSB
mV
mV/°C
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
2
_______________________________________________________________________________________
12-Bit, 170Msps ADC with CMOS
Outputs for Wideband Applications
ELECTRICAL CHARACTERISTICS (continued)
(V
AVCC
= V
OVCC
= 1.8V, V
AGND
= V
OGND
= 0V, f
SAMPLE
= 170MHz, DEMUX = 0, differential LVPECL clock input drive, 0.1µF capac-
itor on REFIO, internal reference, T
A
= T
MIN
to T
MAX
, unless otherwise noted. T
A
≥
+25°C guaranteed by production test, T
A
< +25°C
guaranteed by design and characterization. Typical values are at T
A
= +25°C.)
PARAMETER
CLOCK INPUTS (CLKP, CLKN)
Differential Clock Input
Amplitude
Clock Input Common-Mode
Voltage Range
Clock Differential Input
Resistance
Clock Differential Input
Capacitance
R
CLK
C
CLK
(Note 2)
200
500
1.15
±0.25
11
±25%
5
mV
P-P
V
kΩ
pF
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
MAX19542
DYNAMIC CHARACTERISTICS (at -2dBFS)
f
IN
= 10MHz
Signal-to-Noise Ratio
SNR
f
IN
= 100MHz
f
IN
= 180MHz
f
IN
= 240MHz
f
IN
= 10MHz
Signal-to-Noise and Distortion
SINAD
f
IN
= 100MHz
f
IN
= 180MHz
f
IN
= 240MHz
f
IN
= 10MHz
Spurious-Free Dynamic Range
SFDR
f
IN
= 100MHz
f
IN
= 180MHz
f
IN
= 240MHz
f
IN
= 10MHz
Worst Harmonics
(HD2 or HD3)
f
IN
= 100MHz
f
IN
= 180MHz
f
IN
= 240MHz
Two-Tone Intermodulation
Distortion
IMD
100
f
IN1
= 207.5MHz at -7dBFS,
f
IN2
= 211.5MHz at -7dBFS, f
SAMPLE
= 170MHz
V
OVCC
- 0.1
0.1
0.2 x
V
AVCC
0.8 x
V
AVCC
68.3
68.3
61.9
61.7
62.3
62.3
65
64.3
63.5
63.3
64.8
63.6
62.6
63
82
73
72.4
76.4
-85
-73
-72.4
-76.4
-69
dBc
-69.1
-68.7
dBc
dBc
dB
dB
CMOS DIGITAL OUTPUTS (DA0–DA11, DB0–DB11, ORA, ORB)
Logic-High Output Voltage
Logic-Low Output Voltage
V
OH
V
OL
V
V
LVCMOS DIGITAL INPUTS (CLKDIV,
T/B,
DEMUX, ITL)
Digital Input-Voltage Low
Digital Input-Voltage High
V
IL
V
IH
V
V
_______________________________________________________________________________________
3
12-Bit, 170Msps ADC with CMOS
Outputs for Wideband Applications
MAX19542
ELECTRICAL CHARACTERISTICS (continued)
(V
AVCC
= V
OVCC
= 1.8V, V
AGND
= V
OGND
= 0V, f
SAMPLE
= 170MHz, DEMUX = 0, differential LVPECL clock input drive, 0.1µF capac-
itor on REFIO, internal reference, T
A
= T
MIN
to T
MAX
, unless otherwise noted. T
A
≥
+25°C guaranteed by production test, T
A
< +25°C
guaranteed by design and characterization. Typical values are at T
A
= +25°C.)
PARAMETER
Input Resistance
Input Capacitance
TIMING CHARACTERISTICS
CLKP-to DA0–DA11 Propagation
Delay
CLKP-to-DCLKP Propagation
Delay
DCLKP Rising Edge to
DA0–DA11
CMOS Output Rise Time
CMOS Output Fall Time
RESET Hold
RESET Setup
Output Data Pipeline Delay
POWER REQUIREMENTS
Analog Supply Voltage Range
Digital Supply Voltage Range
Analog Supply Current
Digital Supply Current
Analog Power Dissipation
Power-Supply Rejection Ratio
AVCC
OVCC
I
AVCC
I
OVCC
P
DISS
PSRR
f
IN
= 100MHz
f
IN
= 100MHz
f
IN
= 100MHz
Offset (Note 3)
Gain (Note 3)
1.7
1.7
1.8
1.8
480
24
907
1.8
1.5
1.9
1.9
520
31
992
V
V
mA
mA
mW
mV/V
%FS/V
t
PDL
t
CPDL
t
PDL
-
t
CPDL
t
RISE
t
FALL
t
HR
t
SR
t
LATENCY
Figures 5, 6, and 7
Figures 5, 6, and 7
Figures 5, 6, and 7 (Note 2)
20% to 80%, C
L
= 5pF
20% to 80%, C
L
= 5pF
Figure 4
Figure 4
Figure 4
180
2.5
2.1
400
1
1
100
500
11
710
ns
ns
ns
ns
ns
ps
ps
Clock
cycles
SYMBOL
R
IN
C
IN
CONDITIONS
MIN
TYP
46.5
5
MAX
UNITS
kΩ
pF
Note 1:
Static linearity and offset parameters are computed from a straight line drawn between the end points of the code transition
transfer function. The full-scale range (FSR) is defined as 4096 x slope of the line.
Note 2:
Parameter guaranteed by design and characterization; T
A
= T
MIN
to T
MAX
.
Note 3:
PSRR is measured with both analog and digital supplies connected to the same potential.
4
_______________________________________________________________________________________
12-Bit, 170Msps ADC with CMOS
Outputs for Wideband Applications
Typical Operating Characteristics
(V
AVCC
= V
OVCC
= 1.8V, V
AGND
= V
OGND
= 0V, f
SAMPLE
= 170MHz, A
IN
= -1dBFS; see TOCs for detailed information on test condi-
tions, differential input drive, differential LVPECL clock input drive, 0.1µF capacitor on REFIO, internal reference, digital outputs dif-
ferential R
L
= 100Ω, T
A
= +25°C.)
FFT PLOT
FFT PLOT
FFT PLOT
(16,384-POINT DATA RECORD)
(16,384-POINT DATA RECORD)
(16,384-POINT DATA RECORD)
MAX19542 toc01
MAX19542 toc02
MAX19542
-10
-20
-30
AMPLITUDE (dB)
-40
-50
-60
-70
-80
-90
-100
-110
0
10
20
30
2
AMPLITUDE (dB)
AMPLITUDE (dB)
f
IN
= 12.9599243MHz
f
SAMPLE
= 170.0043234MHz
A
IN
= -1.05dBFS
SNR = 65.923dB
SINAD = 65.822dB
SFDR = 88.137dBc
HD2 = -92.278dBc
HD3 = -88.96dBc
3
4
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
f
IN
= 64.9863939MHz
f
SAMPLE
= 170.0043234MHz
A
IN
= -1.068dBFS
SNR = 65.921dB
SINAD = 65dB
SFDR = 74.007dBc
HD2 = -82.197dBc
HD3 = -79.515dBc
3
5
2
6
7
4
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
7
f
IN
= 190.186111MHz
f
SAMPLE
= 170.0043234MHz
A
IN
= -1.03dBFS
SNR = 64.664dB
SINAD = 63.513dB
SFDR = 71.34dBc
HD2 = -77.559dBc
HD3 = -71.34dBc
2
6
3
5
4
5
67
40
50
60
70
80
0
10
20
30
40
50
60
70
80
0
10
20
30
40
50
60
70
80
ANALOG INPUT FREQUENCY (MHz)
ANALOG INPUT FREQUENCY (MHz)
ANALOG INPUT FREQUENCY (MHz)
FFT PLOT
(16,384-POINT DATA RECORD)
MAX19542 toc04
SNR/SINAD vs. ANALOG INPUT FREQUENCY
(f
SAMPLE
= 170.0043MHz, A
IN
= -1dBFS)
MAX19542 toc05
SFDR vs. ANALOG INPUT FREQUENCY
(f
SAMPLE
= 170.0043MHz, A
IN
= -1dBFS)
85
80
75
SFDR (dBc)
MAX19542 toc06
0
-10
-20
-30
AMPLITUDE (dB)
-40
-50
-60
-70
-80
-90
-100
-110
0
SNR/SINAD (dB)
f
IN
= 241.008937MHz
f
SAMPLE
= 170.0043234MHz
A
IN
= -1.035dBFS
SNR = 64.01dB
SINAD = 63.521dB
SFDR = 74.963dBc
HD2 = -74.963dBc
HD3 = -82.606dBc
2
7 5
3 4
6
70
SNR
90
67
64
SINAD
70
65
60
55
61
58
50
45
55
10
20
30
40
50
60
70
80
0
25 50 75 100 125 150 175 200 225 250
f
IN
(MHz)
ANALOG INPUT FREQUENCY (MHz)
40
0
25 50 75 100 125 150 175 200 225 250
f
IN
(MHz)
HD2/HD3 vs. ANALOG INPUT FREQUENCY
(f
SAMPLE
= 170.0043MHz, A
IN
= -1dBFS)
-40
-45
-50
-55
-60
-65
-70
-75
-80
-85
-90
-95
-100
-105
-110
-115
-120
0
MAX19542 toc07
THD vs. ANALOG INPUT FREQUENCY
(f
SAMPLE
= 170.0043MHz, A
IN
= -1dBFS)
MAX19542 toc08
SNR/SINAD vs. ANALOG INPUT AMPLITUDE
(f
SAMPLE
= 170.0043MHz, f
IN
= 64.9864MHz)
SNR
62
SNR/SINAD (dB)
56
50
44
38
32
SINAD
MAX19542 toc09
-60
-65
-70
THD (dBc)
-75
-80
-85
68
HD3
HD2/HD3 (dBc)
HD2
-90
-95
-100
25 50 75 100 125 150 175 200 225 250
f
IN
(MHz)
0
25 50 75 100 125 150 175 200 225 250
f
IN
(MHz)
-30
-25
-20
-15
A
IN
(dBFS)
-10
-5
0
_______________________________________________________________________________________
MAX19542 toc03
0
0
0
5
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