Dual 2:1, 1:2 Differential-to-LVDS
Multiplexer
ICS854S54I-01
Datasheet
Description
The ICS854S54I-01 is a 2:1/1:2 Multiplexer. The 2:1 Multiplexer
allows one of two inputs to be selected onto one output pin and the
1:2 MUX switches one input to both outputs. This device may be
useful for multiplexing multi-rate Ethernet PHYs which have 100Mbit
and 1000Mbit transmit/receive pairs onto an optical SFP module
which has a single transmit/receive pair. Another mode allows loop
back testing and allows the output of a PHY transmit pair to be routed
to the PHY input pair. For examples, please refer to the Application
Information section of the data sheet.
The ICS854S54I-01 is optimized for applications requiring very high
performance and has a maximum operating frequency of 2.5GHz.
The device is packaged in a small, 3mm x 3mm VFQFN package,
making it ideal for use on space-constrained boards.
Features
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Dual 2:1, 1:2 MUX
Three LVDS output pairs
Three differential clock inputs can accept: LVPECL, LVDS, CML
Loopback test mode available
Maximum output frequency: 2.5GHz
Propagation delay: 600ps (maximum)
Part-to-part skew: 300ps (maximum)
Additive phase jitter, RMS: 0.031ps (typical)
Full 2.5V supply mode
-40°C to 85°C ambient operating temperature
Available in lead-free (RoHS 6) package
Block Diagram
SELB
Pulldown
Pin Assignment
SELA
nQB
QA0 1
nQA0
INA0
nINA0
2
16 15 14 13
12 INA0
11 nINA0
10 INA1
9 nINA1
5
6
nINB
QA1 3
nQA1 4
7
SELB
INB
nINB
LOOP0
0
QA0
nQA0
ICS854S54I-01
16-Lead VFQFN
3mm x 3mm x 0.925mm package body
Top View
0
QB
nQB
1
INA1
1
nINA1
LOOP1
QA1
nQA1
SELA
ICS854S54I-01 July 17, 2017
Pulldown
1
©2017 Integrated Device Technology, Inc.
GND
INB
V
DD
QB
8
ICS854S54I-01 Datasheet
DUAL 2:1, 1:2 DIFFERENTIAL-TO-LVDS MULTIPLEXER
Table 1. Pin Descriptions
Number
1, 2
3, 4
5
6
7
8
9
10
11
12
13
14
15, 16
Name
QA0, nQA0
QA1, nQA1
INB
nINB
SELB
GND
nINA1
INA1
nINA0
INA0
V
DD
SELA
nQB, QB
Output
Output
Input
Input
Input
Power
Input
Input
Input
Input
Power
Input
Output
Pulldown
Pullup/
Pulldown
Pulldown
Pullup/
Pulldown
Pulldown
Pulldown
Pullup/
Pulldown
Pulldown
Type
Description
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
Non-inverting differential clock input.
Inverting differential clock input. V
DD
/2 default when left floating.
Select pin for QAx outputs. When HIGH, selects same inputs used for QB output.
When LOW, selects INB input. LVCMOS/LVTTL interface levels.
Power supply ground.
Inverting differential clock input. V
DD
/2 default when left floating.
Non-inverting differential clock input.
Inverting differential clock input. V
DD
/2 default when left floating.
Non-inverting differential clock input.
Power supply pin.
Select pin for QB outputs. When HIGH, selects INA1 input.
When LOW, selects INA0 input. LVCMOS/LVTTL interface levels.
Differential output pair. LVDS interface levels.
NOTE:
Pullup and Pulldown
refer to internal input resistors. See Table 2,
Pin Characteristics,
for typical values.
Table 2. Pin Characteristics
Symbol
R
PULLUP
Parameter
Input Pullup Resistor
Test Conditions
Minimum
Typical
37.5
37.5
Maximum
Units
k
k
R
PULLDOWN
Input Pulldown Resistor
Function Tables
Table 3. Control Input Function Table
Control Inputs
SELA
0
1
0
1
SELB
0
0
1
1
Mode
LOOP0 selected (default)
LOOP1 selected
Loopback mode: LOOP0
Loopback mode: LOOP1
ICS854S54I-01 July 17, 2017
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©2017 Integrated Device Technology, Inc.
ICS854S54I-01 Datasheet
DUAL 2:1, 1:2 DIFFERENTIAL-TO-LVDS MULTIPLEXER
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under
Absolute Maximum Ratings
may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the
DC Characteristics or AC Characteristics
is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Supply Voltage, V
DD
Inputs, V
I
Outputs, I
O
Continuous Current
Surge Current
Package Thermal Impedance,
JA
Storage Temperature, T
STG
Rating
4.6V
-0.5V to V
DD
+ 0.5V
10mA
15mA
74.7C/W (0 mps)
-65C to 150C
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics,
V
DD
= 2.5V ± 5%, T
A
= -40°C to 85°C
Symbol
V
DD
I
DD
Parameter
Positive Supply Voltage
Power Supply Current
Test Conditions
Minimum
2.375
Typical
2.5
Maximum
2.625
82
Units
V
mA
Table 4B. LVCMOS/LVTTL DC Characteristics,
V
DD
= 2.5V ± 5%, T
A
= -40°C to 85°C
Symbol
V
IH
V
IL
I
IH
I
IL
Parameter
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
SELA, SELB
SELA, SELB
V
DD
= V
IN
= 2.625V
V
DD
= 2.625V, V
IN
= 0V
-150
Test Conditions
Minimum
1.7
0
Typical
Maximum
V
DD
+ 0.3
0.7
150
Units
V
V
µA
µA
Table 4C. DC Characteristics,
V
DD
= 2.5V ± 5%, T
A
= -40°C to 85°C
-40°C
Symbol
I
IH
I
IL
V
PP
V
CMR
Parameter
Input
High Current
Input
Low Current
INAx, INB
nINAx, nINB
INAx, INB
nINAx, nINB
-10
-150
0.15
1.2
1.2
V
DD
Min
Typ
Max
150
-10
-150
0.15
1.2
1.2
V
DD
Min
25°C
Typ
Max
150
-10
-150
0.15
1.2
1.2
V
DD
Min
85°C
Typ
Max
150
Units
µA
µA
µA
V
V
Peak-to-Peak Input Voltage
Common Mode Input Voltage;
NOTE 1
NOTE 1: Common mode input voltage is defined as V
IH.
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ICS854S54I-01 Datasheet
DUAL 2:1, 1:2 DIFFERENTIAL-TO-LVDS MULTIPLEXER
Table 4D. LVDS DC Characteristics,
V
DD
= 2.5V ± 5%, T
A
= -40°C to 85°C
-40°C
Symbol
V
OD
V
OD
V
OS
V
OS
Parameter
Differential Output Voltage
V
OD
Magnitude Change
Offset Voltage
V
OS
Magnitude Change
1.125
1.25
Min
247
Typ
350
Max
454
60
1.375
50
1.125
1.25
Min
247
25°C
Typ
350
Max
454
60
1.375
50
1.125
1.25
Min
247
85°C
Typ
350
Max
454
60
1.375
50
Units
mV
mV
V
mV
NOTE: Refer to Parameter Measurement Information,
2.5V Output Load Test Circuit diagram.
AC Electrical Characteristics
Table 5. AC Characteristics,
V
DD
= 2.5V ± 5%, T
A
= -40°C to 85°C
Symbol
f
OUT
t
PD
tsk(pp)
tjit
t
R
/ t
F
MUX_
ISOLATION
Parameter
Output Frequency
Propagation Delay; NOTE 1
Part-to-Part Skew; NOTE 2, 3
Buffer Additive Phase Jitter, RMS;
refer to Additive Phase Jitter Section
Output Rise/Fall Time
MUX Isolation; NOTE 4
ƒ
OUT
= 622.08MHz,
12kHz – 20MHz
20% to 80%
ƒ
OUT
= 500MHz output,
V
PP
= 400mV
60
65
0.031
300
INAx to QB or INB to QAx
INAx to QAx
250
300
Test Conditions
Minimum
Typical
Maximum
2.5
600
600
300
Units
GHz
ps
ps
ps
ps
ps
dB
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device
is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal
equilibrium has been reached under these conditions.
NOTE: All parameters measured at
1.7GHz unless otherwise noted.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as skew between outputs on different devices operating at the same supply voltage, same temperature and with equal load
conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 4: Q, nQ output measured differentially. See MUX Isolation Diagram in Parameter Measurement Information section.
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©2017 Integrated Device Technology, Inc.
ICS854S54I-01 Datasheet
DUAL 2:1, 1:2 DIFFERENTIAL-TO-LVDS MULTIPLEXER
Additive Phase Jitter
The spectral purity in a band at a specific offset from the fundamental
compared to the power of the fundamental is called the
dBc Phase
Noise.
This value is normally expressed using a Phase noise plot
and is most often the specified plot in many applications. Phase noise
is defined as the ratio of the noise power present in a 1Hz band at a
specified offset from the fundamental frequency to the power value of
the fundamental. This ratio is expressed in decibels (dBm) or a ratio
of the power in the 1Hz band to the power in the fundamental. When
the required offset is specified, the phase noise is called a
dBc
value,
which simply means dBm at a specified offset from the fundamental.
By investigating jitter in the frequency domain, we get a better
understanding of its effects on the desired application over the entire
time record of the signal. It is mathematically possible to calculate an
expected bit error rate given a phase noise plot.
Additive Phase Jitter @ 622.08MHz
12kHz to 20MHz = 0.031ps (typical)
SSB Phase Noise dBc/Hz
Offset from Carrier Frequency (Hz)
As with most timing specifications, phase noise measurements has
issues relating to the limitations of the equipment. Often the noise
floor of the equipment is higher than the noise floor of the device. This
is illustrated above. The device meets the noise floor of what is
shown, but can actually be lower. The phase noise is dependent on
the input source and measurement equipment.
The source generator “IFR2042 10kHz – 56.4GHz Low Noise Signal
Generator as external input to an Agilent 8133A 3GHz Pulse
Generator.
ICS854S54I-01 July 17, 2017
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©2017 Integrated Device Technology, Inc.
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