MIC2310
Single-FET, Constant Power-Limit Hot
Swap Controller
General Description
The MIC2310 is a single-channel, positive voltage,
constant power-limit hot swap controller designed to
provide for the safe insertion and removal of pc boards into
fixed, rack, and pedestal mid- or back-planes using few
external components. In addition, the MIC2310 employs a
patent-pending, output load power-limiting technique
where the current limit is inversely proportional to the
output load voltage, such that the power product will not
exceed the programmed power limit any longer than the
externally programmed primary overcurrent period. The
MIC2310 is ideally suited to address the power-limiting
and timing requirements per the UL60950 specification for
240-VA applications. The MIC2310 incorporates high-side
controller circuitry for an external N-channel MOSFET for
which the MOSFET drain current rate of change is user-
programmable via an external capacitor. The MIC2310
employs dual-speed, dual-level overcurrent fault
protection. The primary overcurrent detector response time
is programmable via an external current sense resistor and
the secondary overcurrent detector is 2-bit user-
programmable and exhibits a very fast (default) response
to faults to ensure that the system power supplies are
protected against catastrophic load current and short-
circuit faults. Additionally, an analog output (voltage) signal
is provided that is proportional to the steady-state load
current to allow monitoring of the system’s power. A
PWRGD signal is provided to indicate a valid output
voltage that can be used to enable a DC-DC power
module.
Data sheets and support documentation can be found on
Micrel’s web site at www.micrel.com.
Features
•
•
Provides safe PCB insertion and removal from live
+12V backplanes
Patent-pending, adaptive circuit breaker threshold
control
– Maintains constant power product at output
– Power-limit product (VA) is externally
programmable for various power applications
Dual-level, dual-speed overcurrent detection/protection
– Programmable primary detector response time
– Fast (< 1
µs)
secondary detector response time to
short circuit conditions
User-programmable threshold settings via (2)
digital inputs
Steady-state load current monitoring
Programmable inrush current slew-rate control
Electronic circuit breaker functions after fault
– Latch off
– Automatic retry
Programmable input undervoltage lockout and
overvoltage protection
Fault reporting:
– Open-drain ‘Power-is-Good’ output
– Open-drain ‘I_FLT’ output signaling for all current
faults
– Shorted R
SENSE
and Damaged MOSFET detection
(D-G and D-S shorts)
•
•
•
•
•
•
Applications
•
•
•
•
•
•
•
UL60950, EN60950, and CSA1950 systems (240-VA)
General Power-limiting Applications
Base stations
Enterprise servers
High-reliability servers
Enterprise switch networks
+12V backplanes
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (
408
) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com
July 2008
M9999-070108-A
Micrel, Inc.
MIC2310
Typical Application
V
IN
12V
R1
C3
0.68µF
C1
1.5µF
6
1
R
SENSE
1
0.5%
2
4
Q1
IRL3713S
D
2
Pak
V
OUT
12V@20A
C2*
3
R2
C4
0.47µF
C7
0.01µF
R3
1%
R4
1%
R5
1%
24
23
22
11
10
21
19
VCC
ENABLE
UVLO
VCCSENSE
SENSE
CSLEW
CPRIMARY
GATE
SOURCE
LOADSENSE
GNDSENSE
18
R9
C
LOAD
17
3
2
OVP
S0
MIC2310
DISCH
VREG
16
7
S[1,0]=X,X
8
4
C
DISCH
C6
0.1µF
Q2
ZUMT618
SOT-323
S1
VISS
CRETRY
9
CPGND
20
AGND
12
HW_FLT
13
PWRGD
14
I_FLT
15
TO SYSTEM
MANAGEMENT
CONTROLLER
3
R8
V
LOGIC
C5
0.068µF
R6
R7
Overcurrent
Fault Output
* The value of C2 is flexible and dependant upon the
parasitic inductance, which should be minimzed as much
as possible. A
inductance) for C2 is 56µF, minimum
Power-Good
Output
Hardware
Fault Output
July 2008
2
M9999-070108-A
Micrel, Inc.
MIC2310
Ordering Information
Part Number
MIC2310-1ZTS
MIC2310-2ZTS
Note:
1. Other Voltage available. Contact Micrel for details.
PWRGD State
Active-HIGH
Active-LOW
I_FLT State
Active-HIGH
Active-LOW
Fault Condition Status
Latched/Auto-retry
Latched/Auto-retry
Package
24-pin TSSOP
24-pin TSSOP
Lead Finish
Pb-Free
Pb-Free
Pin Configuration
UVLO
OVP
VISS
VREG
NC
ENABLE
S0
S1
CRETRY
1
2
3
4
5
6
7
8
9
24 VCC
23 VCCSENSE
22 SENSE
21 GATE
20 CPGND
19 SOURCE
18 LOADSENSE
17 GNDSENSE
16 DISCH
15 I_FLT
14 PWRGD
13 HW_FLT
UVLO
OVP
VISS
VREG
NC
ENABLE
S0
S1
CRETRY
1
2
3
4
5
6
7
8
9
24 VCC
23 VCCSENSE
22 SENSE
21 GATE
20 CPGND
19 SOURCE
18 LOADSENSE
17 GNDSENSE
16 DISCH
15 /I_FLT
14 /PWRGD
13 HW_FLT
CPRIMARY 10
CSLEW 11
AGND 12
CPRIMARY 10
CSLEW 11
AGND 12
24-pin TSSOP (TS)
MIC2310-1ZTS
24-pin TSSOP (TS)
MIC2310-2ZTS
July 2008
3
M9999-070108-A
Micrel, Inc.
MIC2310
Pin Description
Pin Number
1
Pin Name
UVLO
Pin Function
Undervoltage Lockout Input. When the applied voltage at the UVLO pin is higher
than the controller’s V
UVLOH
threshold voltage, the GATE drive circuits are active
when ENABLE= HIGH. If the applied voltage at the UVLO pin falls below the
controller’s V
UVLOL
threshold voltage, the GATE drive circuits are disabled to turn
the external MOSFET OFF. In addition, the DISCH circuit is activated to drive an
optional, external discharge transistor alone (illustrated in the Typical Application
circuit) or in combination with an SCR for a very fast discharge circuit
configuration.
Overvoltage Protection Input. When the applied voltage at the OVP pin is higher
than the controller’s V
OVPH
threshold voltage, the GATE drive circuit is disabled
to turn the external MOSFET OFF. In addition, the DISCH circuit is activated to
drive an optional, external discharge transistor alone (illustrated in the Typical
Application circuit) or in combination with an SCR for a very fast discharge circuit
configuration. Using an external resistor divider, the UVLO and the OVP pins
form a window comparator that defines the supply voltage range within which the
load may be safely powered.
Steady-state Output Current Monitor. This output signal provides an analog
voltage that is proportional to the steady-state load current. This signal is
provided as an input to the system supervisor/processor to monitor the dc
current/power level of the application circuit.
Internal +5V Regulator Bypass. Connect a 0.1-µF, 16V ceramic capacitor from
this pin to AGND.
No connection
ENABLE Input. An active asserted-HIGH digital input that controls the operation
of the MIC2310. Activated after the internal POR timer has terminated, a LOW-
to-HIGH transition on this pin commences a start-up sequence if the applied V
CC
is above the V
UVLOH
and below the V
OVPH
threshold voltages. While ENABLE =
LOW, the GATE pin is held to 0V and the DISCH output is activated. The
ENABLE input can be used to reset the internal circuit breaker by applying a
HIGH-to-LOW-to-HIGH transition as defined by t
ENLPW
following either a load
current fault, an open LOADSENSE fault, an open GNDSENSE fault, or a
shorted RSENSE fault.
Secondary OC Detector Current Threshold Digital Inputs – S1 is the MSB and
S0 is the LSB. When used together, S[1:0] sets the overcurrent threshold for the
secondary overcurrent detection circuit to one of four levels relative to the
primary overcurrent detector nominal threshold. For example, S[1:0] = L, L sets
the secondary overcurrent threshold at 1.3X; S[1:0] = L, H sets a 1.5X threshold;
S[1:0] = H, L sets a 2X threshold, and S[1:0] = H, H sets a 1.75X threshold. If the
S[1:0] pins are not connected or left NC, the default setting is S[1:0] = L, L or
1.3X. The permissible voltage range on these inputs is AGND
≤
S[1:0]
≤
V
CC
.
Auto-retry Timing Capacitor. A capacitor connected from the CRETRY pin to
AGND configures the MIC2310 to re-start automatically with ENABLE = HIGH
after the circuit breaker trips and latches off. It also sets the “cool-off” time delay
before a new load current start-up sequence is initiated. To configure the
MIC2310’s circuit breaker to latch off after fault, connect this pin to AGND. The
circuit breaker latches OFF and remains latched OFF unless the ENABLE input
is toggled HIGH-to-LOW-to-HIGH as defined by t
ENLPW
or the V
CC
supply voltage
is turned OFF then ON.
Primary Overcurrent Detector Timing Capacitor. Connecting a capacitor from the
CPRIMARY pin to AGND sets the response time of the controller’s primary
overcurrent detection circuit to GATE OFF in the event of an overcurrent
condition. If the CPRIMARY pin is not connected, the primary overcurrent
detection response time defaults to t
POCSENSE
, typically 250µs as specified in the
Electrical Characteristics Table. The controller incorporates a patent-pending
built-in test for a faulty CPRIMARY capacitor.
2
OVP
3
VISS
4
5
6
VREG
NC
ENABLE
7
8
S0
S1
9
CRETRY
10
CPRIMARY
July 2008
4
M9999-070108-A
Micrel, Inc.
MIC2310
Pin Description (continued)
Pin Number
11
Pin Name
CSLEW
Pin Function
Inrush Current Slew Rate Control Input. To adjust the inrush load current profile
(controlled dI
DRAIN
/dt), connect a capacitor from this pin to VCC. To adjust the
MOSFET GATE voltage profile (controlled dV
GATE
/dt), leave this pin OPEN
(floating) and connect a capacitor from GATE to AGND. For additional
information on the operation of this function, please refer to the Functional
Description section.
Analog Ground. Connect this pin to the system analog ground plane.
External MOSFET Hardware Fault Digital Output. This output is an open-drain,
active-HIGH signal that should be connected to a +3.3V logic supply by a 10kΩ
resistor. This digital output is active after the internal POR timer has terminated
and becomes asserted (HIGH) due to a fault under the following conditions: a) a
shorted DG MOSFET with ENABLE = LOW; b) a shorted DS MOSFET with
ENABLE = LOW; c) a shorted R
SENSE
; d) a shorted DS MOSFET after steady-
state operation with ENABLE = HIGH-to-LOW; or e) a shorted DG or DS while
EN = HIGH and DISCH = HIGH; or f) a shorted C
PRIMARY
to AGND. The
HW_FLT output is latched and is reset when VCC is brought low such that
V
REG
< V
VREG(UVLO)
.
Power Good Digital Output. This output is an open-drain, active-HIGH (PWRGD)
or active-LOW (/PWRGD) signal that should be connected to a +3.3-V logic
supply by a 10kΩ resistor. This digital output is active after the internal POR
timer has terminated and becomes asserted when the voltage between the
LOADSENSE and the GNDSENSE pins is higher than the controller’s V
PGH
threshold voltage. It is de-asserted when the voltage between the LOADSENSE
and the GNDSENSE pins is less than the controller’s V
PGL
threshold voltage.
Load Current Fault Digital Output. This output is an open-drain, active-HIGH
(I_FLT) or active-LOW (/I_FLT) signal that should be connected to a +3.3V logic
supply by a 10kΩ resistor. This digital output is active after the internal POR
timer has terminated and becomes asserted whenever the primary or secondary
overcurrent detection circuits cause the internal circuit breaker to latch OFF. The
digital output remains asserted unless the ENABLE input is toggled HIGH-to-
LOW-to-HIGH as defined by t
ENLPW
or the V
CC
supply voltage is turned OFF then
ON or if the auto-retry mode is enabled.
Discharge External Transistor Drive Output. When ENABLE = LOW or after a
fault condition (either an overcurrent fault or hardware fault such as a shorted
MOSFET) that causes either the primary and secondary overcurrent detectors to
trip the internal circuit breaker, the DISCH circuit is activated to provide gate
drive to optional, external transistors (and SCR, for very fast load discharge).
These transistors serve as auxiliary gate pull-down or load voltage pull-down
switches. A load voltage pull-down is illustrated in the Typical Application circuit.
These input pins (when used together) sense the load voltage and provide
feedback to the controller’s adaptive VA limit and Power-Good circuits. The
voltage across these two pins also sets the controller’s Power-Is-Good status
output as defined by the specified V
PGH
or the V
PGL
threshold voltages. Internal
circuit monitors are included if either or both LOADSENSE and GNDSENSE
connections are severed or not connected to the load.
External Power MOSFET Source Pin Monitor. To protect external circuits
downstream of the controller, internal monitor circuits are included to sense a
shorted drain-source condition of the external power MOSFETs.
Internal charge pump power ground. Connect this pin directly to the system’s
analog ground plane.
External N-channel MOSFET GATE Drive Output. The GATE output signal uses
an internal charge pump to charge the gate of an external N-channel MOSFET
pass transistor.
12
13
AGND
HW_FLT
14
PWRGD
/PWRGD
15
I_FLT
/I_FLT
16
DISCH
17
18
GNDSENSE
LOADSENSE
19
SOURCE
20
21
CPGND
GATE
July 2008
5
M9999-070108-A
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