INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
•
The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
•
The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
•
The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT280
9-bit odd/even parity
generator/checker
Product specification
File under Integrated Circuits, IC06
December 1990
Philips Semiconductors
Product specification
9-bit odd/even parity generator/checker
FEATURES
•
Word-length easily expanded by cascading
•
Similar pin configuration to the “180” for easy system
up-grading
•
Generates either odd or even parity for nine data bits
•
Output capability: standard
•
I
CC
category: MSI
GENERAL DESCRIPTION
The 74HC/HCT280 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The 74HC/HCT280 are 9-bit parity generators or checkers
commonly used to detect errors in high-speed data
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
°C;
t
r
= t
f
= 6 ns
74HC/HCT280
transmission or data retrieval systems. Both even and odd
parity outputs are available for generating or checking
even or odd parity up to 9 bits.
The even parity output (∑
E
) is HIGH when an even number
of data inputs (I
0
to I
8
) are HIGH. The odd parity output (∑
0
)
is HIGH when an odd number of data inputs are HIGH.
Expansion to larger word sizes is accomplished by tying
the even outputs (∑
E
) of up to nine parallel devices to the
data inputs of the final stage. For a single-chip 16-bit
even/odd parity generator/checker, see
PC74HC/HCT7080.
APPLICATIONS
•
25-line parity generator/checker
•
81-line parity generator/checker
TYPICAL
SYMBOL PARAMETER
t
PHL
/ t
PLH
propagation delay
I
n
to
∑
E
I
n
to
∑
O
C
I
C
PD
Notes
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
µW):
P
D
= C
PD
×
V
CC2
×
f
i
+ ∑
(C
L
×
V
CC2
×
f
o
) where:
f
i
= input frequency in MHz
f
o
= output frequency in MHz
∑
(C
L
×
V
CC2
×
f
o
) = sum of outputs
C
L
= output load capacitance in pF
V
CC
= supply voltage in V
2. For HC the condition is V
I
= GND to V
CC
For HCT the condition is V
I
= GND to V
CC
−
1.5 V
ORDERING INFORMATION
See
“74HC/HCT/HCU/HCMOS Logic Package Information”.
input capacitance
power dissipationcapacitance per package
notes 1 and 2
CONDITIONS
HC
C
L
= 15 pF; V
CC
= 5 V
17
20
3.5
65
18
22
3.5
65
ns
ns
pF
pF
HCT
UNIT
December 1990
2
Philips Semiconductors
Product specification
9-bit odd/even parity generator/checker
PIN DESCRIPTION
PIN NO.
8, 9, 10, 11, 12, 13, 1, 2, 4
5, 6
7
14
SYMBOL
I
0
to I
8
∑
E
,
∑
O
GND
V
CC
NAME AND FUNCTION
data inputs
parity outputs
ground (0 V)
positive supply voltage
74HC/HCT280
Fig.1 Pin configuration.
Fig.2 Logic symbol.
Fig.3 IEC logic symbol.
December 1990
3
Philips Semiconductors
Product specification
9-bit odd/even parity generator/checker
DC CHARACTERISTICS FOR 74HC
For the DC characteristics see
“74HC/HCT/HCU/HCMOS Logic Family Specifications”.
Out put capability: standard
I
CC
category: MSI
AC CHARACTERISTICS FOR 74HC
GND = 0 V; t
r
= t
f
= 6 ns; C
L
= 50 pF
T
amb
(°C)
74HC
SYMBOL PARAMETER
min.
t
PHL
/ t
PLH
propagation delay
I
n
to
∑
E
propagation delay
I
n
to
∑
O
output transition time
+25
typ.
55
20
16
63
23
18
19
7
6
−40
to
+85
max. min.
200
40
34
200
40
34
75
15
13
max.
250
50
43
250
50
43
95
19
16
−40
to
+125
min.
max.
300
60
51
300
60
51
110
22
19
ns
UNIT
74HC/HCT280
TEST CONDITIONS
V
CC
(V)
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
WAVEFORMS
Fig.6
t
PHL
/ t
PLH
ns
Fig.6
t
THL
/ t
TLH
ns
Fig.6
December 1990
5
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