MC14555B, MC14556B
Dual Binary to 1-of-4
Decoder/Demultiplexer
The MC14555B and MC14556B are constructed with
complementary MOS (CMOS) enhancement mode devices. Each
Decoder/Demultiplexer has two select inputs (A and B), an active low
Enable input (E), and four mutually exclusive outputs (Q0, Q1, Q2,
Q3). The MC14555B has the selected output go to the “high” state,
and the MC14556B has the selected output go to the “low” state.
Expanded decoding such as binary−to−hexadecimal (1−of−16), etc.,
can be achieved by using other MC14555B or MC14556B devices.
Applications include code conversion, address decoding, memory
selection control, and demultiplexing (using the Enable input as a data
input) in digital data transmission systems.
Features
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1
SOIC−16
D SUFFIX
CASE 751B
1
SOEIAJ−16
F SUFFIX
CASE 966
•
•
•
•
•
•
Diode Protection on All Inputs
Active High or Active Low Outputs
Expandable
Supply Voltage Range = 3.0 Vdc to 18 Vdc
All Outputs Buffered
Capable of Driving Two Low−Power TTL Loads or One Low−Power
Schottky TTL Load Over the Rated Temperature Range
•
NLV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
•
These Devices are Pb−Free and are RoHS Compliant
MAXIMUM RATINGS
(Voltages Referenced to V
SS
)
Parameter
DC Supply Voltage Range
Input or Output Voltage Range
(DC or Transient)
Input or Output Current (DC or Transient)
per Pin
Power Dissipation, per Package (Note 1)
Ambient Temperature Range
Storage Temperature Range
Lead Temperature (8−Second Soldering)
Symbol
V
DD
V
in
, V
out
I
in
, I
out
P
D
T
A
T
stg
T
L
Value
−0.5 to +18.0
−0.5 to V
DD
+ 0.5
±10
500
−55 to +125
−65 to +150
260
Unit
V
V
mA
mW
°C
°C
°C
PIN ASSIGNMENTS
E
A
A
A
B
A
Q0
A
Q1
A
Q2
A
Q3
A
V
SS
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
DD
E
B
A
B
B
B
Q0
B
Q1
B
Q2
B
Q3
B
E
A
A
A
B
A
Q0
A
Q1
A
Q2
A
Q3
A
V
SS
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
DD
E
B
A
B
B
B
Q0
B
Q1
B
Q2
B
Q3
B
MC14555B
MC14556B
MARKING DIAGRAMS
16
1455xBG
AWLYWW
1
SOIC−16
16
MC1455xB
ALYWG
1
SOEIAJ−16
x
A
WL, L
YY, Y
WW, W
G
= 5 or 6
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
1. Temperature Derating: “D/DW” Packages: –7.0 mW/°C From 65°C To 125°C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high−impedance circuit. For proper operation, V
in
and V
out
should be constrained
to the range V
SS
≤
(V
in
or V
out
)
≤
V
DD
.
Unused inputs must always be tied to an appropriate logic voltage level
(e.g., either V
SS
or V
DD
). Unused outputs must be left open.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 4 of this data sheet.
©
Semiconductor Components Industries, LLC, 2014
1
July, 2014 − Rev. 11
Publication Order Number:
MC14555B/D
MC14555B, MC14556B
TRUTH TABLE
Inputs
Enable
E
0
0
0
0
1
Select
B
0
0
1
1
X
A
0
1
0
1
X
0
0
0
1
0
Outputs
MC14555B
0
0
1
0
0
0
1
0
0
0
1
0
0
0
0
1
1
1
0
1
MC14556B
1
1
0
1
1
1
0
1
1
1
0
1
1
1
1
Q3 Q2 Q1 Q0 Q3 Q2 Q1 Q0
BLOCK DIAGRAM
MC14555B
2
3
1
A
B
E
Q0
Q1
Q2
Q3
4
5
6
7
2
3
1
MC14556B
A
B
E
Q0
Q1
Q2
Q3
4
5
6
7
14
X = Don’t Care
A
B
E
13
15
Q0
Q1
Q2
Q3
12
11
10
9
V
DD
= PIN 16
V
SS
= PIN 8
14
13
15
A
B
E
Q0
Q1
Q2
Q3
12
11
10
9
ELECTRICAL CHARACTERISTICS
(Voltages Referenced to V
SS
)
− 55°C
Characteristic
Output Voltage
V
in
= V
DD
or 0
“0” Level
Symbol
V
OL
V
DD
Vdc
5.0
10
15
5.0
10
15
5.0
10
15
V
IH
5.0
10
15
I
OH
Source
5.0
5.0
10
15
I
OL
5.0
10
15
15
−
5.0
10
15
5.0
10
15
–3.0
–0.64
–1.6
–4.2
0.64
1.6
4.2
−
−
−
−
−
−
−
−
−
−
−
−
±0.1
−
5.0
10
20
–2.4
–0.51
–1.3
–3.4
0.51
1.3
3.4
−
−
−
−
−
–4.2
–0.88
–2.25
–8.8
0.88
2.25
8.8
±0.00001
5.0
0.005
0.010
0.015
−
−
−
−
−
−
−
±0.1
7.5
5.0
10
20
–1.7
–0.36
–0.9
–2.4
0.36
0.9
2.4
−
−
−
−
−
−
−
−
−
−
−
−
±1.0
−
150
300
600
mAdc
3.5
7.0
11
−
−
−
3.5
7.0
11
2.75
5.50
8.25
−
−
−
3.5
7.0
11
−
−
−
mAdc
Min
−
−
−
4.95
9.95
14.95
−
−
−
Max
0.05
0.05
0.05
−
−
−
1.5
3.0
4.0
Min
−
−
−
4.95
9.95
14.95
−
−
−
25°C
Typ
(Note 2)
0
0
0
5.0
10
15
2.25
4.50
6.75
Max
0.05
0.05
0.05
−
−
−
1.5
3.0
4.0
125°C
Min
−
−
−
4.95
9.95
14.95
−
−
−
Max
0.05
0.05
0.05
−
−
−
1.5
3.0
4.0
Vdc
Unit
Vdc
“1” Level
V
in
= 0 or V
DD
Input Voltage
“0” Level
(V
O
= 4.5 or 0.5 Vdc)
(V
O
= 9.0 or 1.0 Vdc)
(V
O
= 13.5 or 1.5 Vdc)
“1” Level
(V
O
= 0.5 or 4.5 Vdc)
(V
O
= 1.0 or 9.0 Vdc)
(V
O
= 1.5 or 13.5 Vdc)
Output Drive Current
(V
OH
= 2.5 Vdc)
(V
OH
= 4.6 Vdc)
(V
OH
= 9.5 Vdc)
(V
OH
= 13.5 Vdc)
(V
OL
= 0.4 Vdc)
(V
OL
= 0.5 Vdc)
(V
OL
= 1.5 Vdc)
Input Current
Input Capacitance, (V
in
= 0)
Quiescent Current (Per Package)
V
OH
Vdc
V
IL
Vdc
Sink
I
in
C
in
I
DD
mAdc
pF
mAdc
Total Supply Current (Notes 3, 4)
(Dynamic plus Quiescent,
Per Package)
(C
L
= 50 pF on all outputs, all
buffers switching)
I
T
I
T
= (0.85
mA/kHz)
f + I
DD
I
T
= (1.70
mA/kHz)
f + I
DD
I
T
= (2.60
mA/kHz)
f + I
DD
mAdc
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
2. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
3. The formulas given are for the typical characteristics only at 25°C.
4. To calculate total supply current at loads other than 50 pF: I
T
(C
L
) = I
T
(50 pF) + (C
L
– 50) Vfk where: I
T
is in
mA
(per package), C
L
in pF,
V = (V
DD
– V
SS
) in volts, f in kHz is input frequency, and k = 0.002.
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2
MC14555B, MC14556B
SWITCHING CHARACTERISTICS
(Note 5) (C
L
= 50 pF, T
A
= 25°C)
Characteristic
Output Rise and Fall Time
t
TLH
, t
THL
= (1.5 ns/pF) C
L
+ 25 ns
t
TLH
, t
THL
= (0.75 ns/pF) C
L
+ 12.5 ns
t
TLH
, t
THL
= (0.55 ns/pF) C
L
+ 9.5 ns
Propagation Delay Time − A, B to Output
t
PLH
, t
PHL
= (1.7 ns/pF) C
L
+ 135 ns
t
PLH
, t
PHL
= (0.66 ns/pF) C
L
+ 62 ns
t
PLH
, t
PHL
= (0.5 ns/pF) C
L
+ 45 ns
Propagation Delay Time − E to Output
t
PLH
, t
PHL
= (1.7 ns/pF) C
L
+ 115 ns
t
PLH
, t
PHL
= (0.66 ns/pF) C
L
+ 52 ns
t
PLH
, t
PHL
= (0.5 ns/pF) C
L
+ 40 ns
Symbol
t
TLH
,
t
THL
V
DD
5.0
10
15
5.0
10
15
5.0
10
15
Min
−
−
−
−
−
−
−
−
−
Typ
(Note 6)
100
50
40
220
95
70
200
85
65
Max
200
100
80
ns
440
190
140
ns
400
170
130
Unit
ns
t
PLH
,
t
PHL
t
PLH
,
t
PHL
5. The formulas given are for the typical characteristics only at 25°C.
6. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
INPUT E LOW
20 ns
20 ns
90%
50%
10%
V
DD
V
SS
V
DD
V
SS
V
OH
V
OL
20 ns
INPUT B
t
PHL
OUTPUT Q3
MC14556B
t
THL
t
PLH
OUTPUT Q3
MC14555B
t
TLH
90%
50%
10%
90%
50%
10%
INPUT A HIGH, INPUT E LOW
20 ns
90%
50%
10%
t
PLH
V
DD
V
SS
V
OH
A INPUTS
(50% DUTY CYCLE)
1
2f
B INPUTS
(50% DUTY CYCLE)
t
PHL
V
t
TLH OL
V
OH
V
OL
t
THL
OUTPUT Q1
All 8 outputs connect to respective C
L
loads.
f in respect to a system clock.
Figure 1. Dynamic Power Dissipation Signal Waveforms
Figure 2. Dynamic Signal Waveforms
LOGIC DIAGRAM
(1/2 of Dual)
*
A
*
B
*
E
*
*Eliminated for MC14555B
Q3
Q2
Q1
Q0
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