74AC109, 74ACT109 Dual JK Positive Edge-Triggered Flip-Flop
March 2007
74AC109, 74ACT109
Dual JK Positive Edge-Triggered Flip-Flop
Features
■
I
CC
reduced by 50%
■
Outputs source/sink 24mA
■
ACT109 has TTL-compatible inputs
tm
General Description
The AC/ACT109 consists of two high-speed completely
independent transition clocked JK flip-flops. The clocking
operation is independent of rise and fall times of the
clock waveform. The JK design allows operation as a
D-Type flip-flop (refer to AC/ACT74 data sheet) by
connecting the J and K inputs together.
Asynchronous Inputs:
–
–
–
–
LOW input to S
D
(Set) sets Q to HIGH level
LOW input to C
D
(Clear) sets Q to LOW level
Clear and Set are independent of clock
Simultaneous LOW on C
D
and S
D
makes both
Q and Q HIGH
Ordering Information
Order
Number
74AC109SC
74AC109SJ
74AC109MTC
74ACT109SC
74AC109MTC
74ACT109PC
Package
Number
M16A
M16D
MTC16
M16A
MTC16
N16E
Package Description
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Wide
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Wide
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.
Connection Diagram
Pin Descriptions
Pin Names
J
1
, J
2
, K
1
, K
2
CP
1
, CP
2
C
D1
, C
D2
S
D1
, S
D2
Q
1
, Q
2
, Q
1
, Q
2
Description
Data Inputs
Clock Pulse Inputs
Direct Clear Inputs
Direct Set Inputs
Outputs
FACT™ is a trademark of Fairchild Semiconductor Corporation
.
©1988 Fairchild Semiconductor Corporation
74AC109, 74ACT109 Rev. 1.5
www.fairchildsemi.com
74AC109, 74ACT109 Dual JK Positive Edge-Triggered Flip-Flop
Logic Symbols
IEEE/IEC
Truth Table
Each half.
Inputs
S
D
L
H
L
H
H
H
H
H
Outputs
J
X
X
X
L
H
L
H
C
D
H
L
L
H
H
H
H
H
CP
X
X
X
K
X
X
X
L
L
H
H
X
Q
H
L
H
L
Toggle
Q
0
H
Q
0
Q
L
H
H
H
Q
0
L
Q
0
L
X
H
=
HIGH Voltage Level
L
=
LOW Voltage Level
=
LOW-to-HIGH Transition
X
=
Immaterial
Q
0
(Q
0
)
=
Previous Q
0
(Q
0
) before LOW-to-HIGH Transition of Clock
Logic Diagram
One half shown.
Please note that this diagram is provided only for the understanding of logic operations and should not be used to
estimate propagation delays.
©1988 Fairchild Semiconductor Corporation
74AC109, 74ACT109 Rev. 1.5
www.fairchildsemi.com
2
74AC109, 74ACT109 Dual JK Positive Edge-Triggered Flip-Flop
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
Symbol
V
CC
I
IK
Supply Voltage
DC Input Diode Current
V
I
=
–0.5V
V
I
=
V
CC
+ 0.5V
V
I
I
OK
DC Input Voltage
DC Output Diode Current
V
O
=
–0.5V
V
O
=
V
CC
+ 0.5V
V
O
I
O
DC Output Voltage
Parameter
Rating
–0.5V to +7.0V
–20mA
+20mA
–0.5V to V
CC
+ 0.5V
–20mA
+20mA
–0.5V to V
CC
+ 0.5V
±50mA
±50mA
–65°C to +150°C
140°C
DC Output Source or Sink Current
I
CC
or I
GND
DC V
CC
or Ground Current per Output Pin
T
STG
Storage Temperature
T
J
Junction Temperature
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to absolute maximum ratings.
Symbol
V
CC
Supply Voltage
AC
ACT
V
I
V
O
T
A
∆
V /
∆
t
∆
V /
∆
t
Input Voltage
Output Voltage
Operating Temperature
Parameter
Rating
2.0V to 6.0V
4.5V to 5.5V
0V to V
CC
0V to V
CC
–40°C to +85°C
125mV/ns
125mV/ns
Minimum Input Edge Rate, AC Devices:
V
IN
from 30% to 70% of V
CC
, V
CC
@ 3.3V, 4.5V, 5.5V
Minimum Input Edge Rate, ACT Devices:
V
IN
from 0.8V to 2.0V, V
CC
@ 4.5V, 5.5V
©1988 Fairchild Semiconductor Corporation
74AC109, 74ACT109 Rev. 1.5
www.fairchildsemi.com
3
74AC109, 74ACT109 Dual JK Positive Edge-Triggered Flip-Flop
DC Electrical Characteristics for AC
Symbol
V
IH
Parameter
Minimum HIGH
Level Input Voltage
V
CC
(V)
3.0
4.5
5.5
3.0
4.5
5.5
3.0
4.5
5.5
T
A
=
+25°C
Conditions
V
OUT
=
0.1V
or V
CC
– 0.1V
V
OUT
=
0.1V
or V
CC
– 0.1V
I
OUT
=
–50µA
T
A
=
–40°C to +85°C
Guaranteed Limits
Units
V
2.1
3.15
3.85
0.9
1.35
1.65
2.9
4.4
5.4
2.46
3.76
4.76
0.1
0.1
0.1
0.44
0.44
0.44
±1.0
75
–75
µA
mA
mA
µA
V
V
V
Typ.
1.5
2.25
2.75
1.5
2.25
2.75
2.99
4.49
5.49
2.1
3.15
3.85
0.9
1.35
1.65
2.9
4.4
5.4
2.56
3.86
4.86
V
IL
Maximum LOW
Level Input Voltage
V
OH
Minimum HIGH
Level Output Voltage
V
IN
=
V
IL
or V
IH
:
3.0
4.5
5.5
V
OL
Maximum LOW
Level Output Voltage
3.0
4.5
5.5
V
IN
=
V
IL
or V
IH
:
3.0
4.5
5.5
I
IN(3)
I
OLD
I
OHD
I
CC(3)
Maximum Input
Leakage Current
Minimum Dynamic
Output Current
(2)
Maximum Quiescent
Supply Current
5.5
5.5
5.5
I
OL
=
12mA
I
OL
=
24mA
I
OL
=
24mA
(1)
V
I
=
V
CC
, GND
V
OLD
=
1.65V Max.
V
OHD
=
3.85V Min.
V
IN
=
V
CC
or GND
2.0
0.36
0.36
0.36
±0.1
I
OH
=
–12mA
I
OH
=
–24mA
I
OH
=
–24mA
(1)
I
OUT
=
50µA
0.002
0.001
0.001
0.1
0.1
0.1
20.0
Notes:
1. All outputs loaded; thresholds on input associated with output under test.
2. Maximum test duration 2.0ms, one output loaded at a time.
3. I
IN
and I
CC
@ 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V V
CC
.
©1988 Fairchild Semiconductor Corporation
74AC109, 74ACT109 Rev. 1.5
www.fairchildsemi.com
4
74AC109, 74ACT109 Dual JK Positive Edge-Triggered Flip-Flop
DC Electrical Characteristics for ACT
Symbol
V
IH
V
IL
V
OH
Parameter
Minimum HIGH
Level Input Voltage
Maximum LOW
Level Input Voltage
Minimum HIGH
Level Output
Voltage
V
CC
(V)
4.5
5.5
4.5
5.5
4.5
5.5
T
A
=
+25°C
Conditions
V
OUT
=
0.1V or
V
CC
– 0.1V
V
OUT
=
0.1V or
V
CC
– 0.1V
I
OUT
=
–50µA
V
IN
=
V
IL
or V
IH
:
T
A
=
–40°C to +85°C
Units
V
V
V
2.0
2.0
0.8
0.8
4.4
5.4
3.76
4.76
0.1
0.1
0.44
0.44
± 1.0
1.5
75
–75
µA
mA
mA
mA
µA
V
Typ.
1.5
1.5
1.5
1.5
4.49
5.49
2.0
2.0
0.8
0.8
4.4
5.4
Guaranteed Limits
4.5
5.5
V
OL
Maximum LOW
Level Output
Voltage
4.5
5.5
I
OH
=
–24mA
I
OH
=
–24mA
(4)
I
OUT
=
50µA
V
IN
=
V
IL
or V
IH
:
0.001
0.001
I
OL
=
24mA
I
OL
=
24mA
(4)
V
I
=
V
CC
, GND
V
I
=
V
CC
– 2.1V
V
OLD
=
1.65V Max.
V
OHD
=
3.85V Min.
V
IN
=
V
CC
or GND
0.6
3.86
4.86
0.1
0.1
0.36
0.36
±0.1
4.5
5.5
I
IN
I
CCT
I
OLD
I
OHD
I
CC
Maximum Input
Leakage Current
Maximum I
CC
/Input
Minimum Dynamic
Output Current
(5)
Maximum
Quiescent Supply
Current
5.5
5.5
5.5
5.5
2.0
20.0
Notes:
4. All outputs loaded; thresholds on input associated with output under test.
5. Maximum test duration 2.0ms, one output loaded at a time.
©1988 Fairchild Semiconductor Corporation
74AC109, 74ACT109 Rev. 1.5
www.fairchildsemi.com
5
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