CAT25M02
EEPROM Serial 2-Mb SPI
Description
The CAT25M02 is a EEPROM Serial 2−Mb SPI device internally
organized as 256Kx8 bits. This features a 256−byte page write buffer
and supports the Serial Peripheral Interface (SPI) protocol. The device
is enabled through a Chip Select (CS) input. In addition, the required
bus signals are clock input (SCK), data input (SI) and data output (SO)
lines. The HOLD input may be used to pause any serial
communication with the CAT25M02 device. The device features
software and hardware write protection, including partial as well as
full array protection.
On−Chip ECC (Error Correction Code) makes the device suitable
for high reliability applications.
Features
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SOIC−8
V SUFFIX
CASE 751BD
WLCSP−8
C8A SUFFIX
CASE 567NM
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5 / 10 MHz SPI Compatible
Supply Voltage Range: 1.7 V to 5.5 V
SPI Modes (0,0) & (1,1)
256−byte Page Write Buffer
Additional Identification Page with Permanent Write Protection
Self−timed Write Cycle
Hardware and Software Protection
Block Write Protection – Protect 1/4, 1/2 or Entire EEPROM Array
Low Power CMOS Technology
1,000,000 Program/Erase Cycles
100 Year Data Retention
Industrial and Extended Temperature Range
8−lead SOIC and 8−ball WLCSP Packages and Die Sales*
These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
V
CC
CS
SI
CS
WP
HOLD
SCK
CAT25M02
SO
SO
WP
V
SS
SI
SCK
V
SS
HOLD
V
CC
PIN CONFIGURATIONS
V
CC
CS
1
HOLD
SO
WP
SCK
V
SS
SI
SOIC (V) (Top View)
V
CC
HOLD
SCK
SI
CS
SO
WP
V
SS
WLCSP (C8A) (Top View)
PIN FUNCTION
Pin Name
Function
Chip Select
Serial Data Output
Write Protect
Ground
Serial Data Input
Serial Clock
Hold Transmission Input
Power Supply
Figure 1. Functional Symbol
*Please contact factory for Die Sales Information
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 11 of this data sheet.
©
Semiconductor Components Industries, LLC, 2014
June, 2018
−
Rev. 3
1
Publication Order Number:
CAT25M02/D
CAT25M02
DEVICE MARKINGS
25M02A
AYMZZZ
2MSA
ALYW
WLCSP−8 Package
2MSA = Specific Device Code
A = Assembly Site
L = Wafer Lot Number
Y = Year of Production, Last Number
W = Work Week Number
SOIC−8 Package
25M02A = Specific Device Code
A = Assembly Site
Y = Year of Production, Last Number
M = Assembly Operation Month
ZZZ = Assembly Lot Number, Last Three Numbers
Table 1. ABSOLUTE MAXIMUM RATINGS
Parameters
Operating Temperature
Storage Temperature
Voltage on any Pin with Respect to Ground (Note 1)
Ratings
–40 to +125
–65 to +150
–0.5 to +6.5
Units
°C
°C
V
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. The DC input voltage on any pin should not be lower than
−0.5
V or higher than V
CC
+ 0.5 V. During transitions, the voltage on any pin may
undershoot to no less than
−1.5
V or overshoot to no more than V
CC
+ 1.5 V, for periods of less than 20 ns.
Table 2. RELIABILITY CHARACTERISTICS
(Note 4)
Symbol
N
END
(Notes 2, 3)
T
DR
Endurance
Data Retention
Parameter
Min
1,000,000
100
Units
Program/Erase Cycles
Years
2. Page Mode, V
CC
= 5 V, 25°C.
3. The device uses ECC (Error Correction Code) logic with 6 ECC bits to correct one bit error in 4 data bytes. Therefore, when a single byte
has to be written, 4 bytes (including the ECC bits) are re−programmed. It is recommended to write by multiple of 4 bytes located at addresses
4N, 4(N+1), 4(N+2), 4(N+3), in order to benefit from the maximum number of write cycles.
4. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100
and JEDEC test methods.
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CAT25M02
Table 3. D. C. OPERATING CHARACTERISTICS
Symbol
I
CCR
Parameter
Supply Current
(Read Mode)
Read, SO open /
−40°C
to +85°C
(V
CC
= 1.7 V to 5.5 V, T
A
=
−40°C
to +85°C and V
CC
= 2.5 V to 5.5 V, T
A
=
−40°C
to +125°C, unless otherwise specified)
Test Conditions
V
CC
= 1.7 V, f
SCK
= 5 MHz
V
CC
= 2.5 V, f
SCK
= 10 MHz
V
CC
= 5.5 V, f
SCK
= 10 MHz
Read, SO open /
−40°C
to +125°C
I
CCW
Supply Current
(Write Mode)
Write, CS = V
CC
/
−40°C
to +85°C
Write, CS = V
CC
/
−40°C
to +125°C
I
SB1
(Note 5)
Standby Current
V
IN
= GND or V
CC
,
CS = V
CC
, WP = V
CC
,
HOLD = V
CC
,
V
CC
= 5.5 V
V
IN
= GND or V
CC
,
CS = V
CC
, WP = GND,
HOLD = GND,
V
CC
= 5.5 V
V
IN
= GND or V
CC
CS = V
CC
V
OUT
= GND or V
CC
V
CC
≥
2.5 V
V
CC
≥
2.5 V
V
CC
< 2.5 V
V
CC
< 2.5 V
V
CC
≥
2.5 V, I
OL
= 3.0 mA
V
CC
≥
2.5 V, I
OH
=
−1.6
mA
V
CC
< 2.5 V, I
OL
= 150
mA
V
CC
< 2.5 V, I
OH
=
−100
mA
V
CC
−
0.2V
V
CC
−
0.8V
0.2
2.5 V < V
CC
< 5.5 V,
f
SCK
= 10 MHz
1.7 V < V
CC
< 5.5 V
2.5 V < V
CC
< 5.5 V
T
A
=
−40°C
to +85°C
T
A
=
−40°C
to +125°C
T
A
=
−40°C
to +85°C
T
A
=
−40°C
to +125°C
−2
−2
−0.5
0.7V
CC
−0.5
0.75V
CC
Min
Max
1.2
1.6
2
2
2
2
2
4
3
5
2
2
0.3V
CC
V
CC
+ 0.5
0.25V
CC
V
CC
+ 0.5
0.4
Units
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
V
V
V
V
V
V
V
V
I
SB2
(Note 5)
Standby Current
I
L
I
LO
V
IL1
V
IH1
V
IL2
V
IH2
V
OL1
V
OH1
V
OL2
V
OH2
Input Leakage Current
Output Leakage
Current
Input Low Voltage
Input High Voltage
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
Output Low Voltage
Output High Voltage
5. When not driven, the WP and HOLD inputs are pulled up to V
CC
internally. For noisy environments, when the pin is not used, it is
recommended the WP and HOLD input to be tied to V
CC
, either directly or through a resistor.
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CAT25M02
Table 4. A.C. CHARACTERISTICS
(V
CC
= 1.7 V to 5.5 V, T
A
=
−40°C
to +85°C and V
CC
= 2.5 V to 5.5 V, T
A
=
−40°C
to +125°C, unless otherwise specified.) (Note 6)
V
CC
= 1.7 V
−
5.5 V
Symbol
f
SCK
t
SU
t
H
t
WH
t
WL
t
LZ
t
RI
(Note 7)
t
FI
(Note 7)
t
HD
t
CD
t
V
t
HO
t
DIS
t
HZ
t
CS
t
CSS
t
CSH
t
CNS
t
CNH
t
WPS
t
WPH
t
WC
(Notes 9, 10)
Parameter
Clock Frequency
Data Setup Time
Data Hold Time
SCK High Time
SCK Low Time
HOLD to Output Low Z
Input Rise Time
Input Fall Time
HOLD Setup Time
HOLD Hold Time
Output Valid from Clock Low
Output Hold Time
Output Disable Time
HOLD to Output High Z
CS High Time
CS Setup Time
CS Hold Time
CS Inactive Setup Time
CS Inactive Hold Time
WP Setup Time
WP Hold Time
Write Cycle Time
80
60
60
60
60
20
20
6
0
50
100
40
30
30
30
30
10
10
6
0
10
75
0
20
25
Min
DC
20
20
75
75
50
2
2
0
10
40
Max
5
V
CC
= 2.5 V
−
5.5 V
Min
DC
10
10
40
40
25
2
2
Max
10
Units
MHz
ns
ns
ns
ns
ns
ms
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
Table 5. POWER−UP TIMING
(Notes 7, 8)
Symbol
t
PUR,
t
PUW
Power−up to Read / Write Operation
Parameter
Max
0.1
Units
ms
6. AC Test Conditions:
Input Pulse Voltages: 0.3 V
CC
to 0.7 V
CC
Input rise and fall times:
≤
10 ns
Input and output reference voltages: 0.5 V
CC
Output load: current source I
OL max
/I
OH max
; C
L
= 30 pF
7. This parameter is tested initially and after a design or process change that affects the parameter.
8. t
PUR
and t
PUW
are the delays required from the time V
CC
is stable until the specified operation can be initiated.
9. t
WC
is the time from the rising edge of CS after a valid write sequence to the end of the internal write cycle.
10. The t
WC
time can be set by the user to allow faster internal writes (max 3 ms) by setting the t
WC
bit from the Status Register. The fast write
mode is recommended for V
CC
> 2.5 V.
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CAT25M02
Pin Description
Functional Description
SI:
The serial data input pin accepts op−codes, addresses
and data. In SPI modes (0,0) and (1,1) input data is latched
on the rising edge of the SCK clock input.
SO:
The serial data output pin is used to transfer data out of
the device. In SPI modes (0,0) and (1,1) data is shifted out
on the falling edge of the SCK clock.
SCK:
The serial clock input pin accepts the clock provided
by the host and used for synchronizing communication
between host and CAT25M02.
CS:
The chip select input pin is used to enable/disable the
CAT25M02. When CS is high, the SO output is tri−stated
(high impedance) and the device is in Standby Mode (unless
an internal write operation is in progress).
Every
communication session between host and CAT25M02 must
be preceded by a high to low transition and concluded with
a low to high transition of the CS input.
WP:
The write protect input pin will allow all write
operations to the device when held high. When WP pin is
tied low and the WPEN bit in the Status Register (refer to
Status Register description, later in this Data Sheet) is set to
“1”, writing to the Status Register is disabled.
HOLD:
The HOLD input pin is used to pause transmission
between host and CAT25M02, without having to retransmit
the entire sequence at a later time. To pause, HOLD must be
taken low and to resume it must be taken back high, with the
SCK input low during both transitions. When not used for
pausing, it is recommended the HOLD input to be tied to
V
CC
, either directly or through a resistor.
The CAT25M02 device supports the Serial Peripheral
Interface (SPI) bus protocol, modes (0,0) and (1,1). The
device contains an 8−bit instruction register. The instruction
set and associated op−codes are listed in Table 6.
Reading data stored in the CAT25M02 is accomplished by
simply providing the READ command and an address.
Writing to the CAT25M02, in addition to a WRITE
command, address and data, also requires enabling the
device for writing by first setting certain bits in a Status
Register, as will be explained later.
After a high to low transition on the CS input pin, the
CAT25M02 will accept any one of the six instruction
op−codes listed in Table 6 and will ignore all other possible
8−bit combinations. The communication protocol follows
the timing from Figure 2.
The CAT25M02 features an additional Identification
Page (256 bytes) which can be accessed for Read and Write
operations when the IPL bit from the Status Register is set
to “1”. The user can also choose to make the Identification
Page permanent write protected by setting the LIP bit from
the Status Register (LIP=“1”).
Table 6. INSTRUCTION SET
Instruction
WREN
WRDI
RDSR
WRSR
READ
WRITE
Opcode
0000 0110
0000 0100
0000 0101
0000 0001
0000 0011
0000 0010
Operation
Enable Write Operations
Disable Write Operations
Read Status Register
Write Status Register
Read Data from Memory
Write Data to Memory
Figure 2. Synchronous Data Timing
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