IS42VM83200D / IS42VM16160D / IS42VM32800D
32Mx8, 16Mx16, 8Mx32
256Mb Mobile Synchronous DRAM
FEATURES
• Fully synchronous; all signals referenced to a
positive clock edge
• Internal bank for hiding row access and pre-
charge
• Programmable CAS latency: 2, 3
• Programmable Burst Length: 1, 2, 4, 8, and Full
Page
• Programmable Burst Sequence:
• Sequential and Interleave
• Auto Refresh (CBR)
• TCSR (Temperature Compensated Self Refresh)
• PASR (Partial Arrays Self Refresh): 1/16, 1/8,
1/4, 1/2, and Full
• Deep Power Down Mode (DPD)
• Driver Strength Control (DS): 1/4, 1/2, and Full
APRIL 2012
DESCRIPTION
ISSI's 256Mb Mobile Synchronous DRAM achieves high-
speed data transfer using pipeline architecture. All input
and output signals refer to the rising edge of the clock
input. Both write and read accesses to the SDRAM are
burst oriented. The 256Mb Mobile Synchronous DRAM
is designed to minimize current consumption making it
ideal for low-power applications. Both TSOP and BGA
packages are offered, including industrial grade products.
KEY TIMING PARAMETERS
Parameter
CLK Cycle Time
CAS
Latency = 3
CAS
Latency = 2
CLK Frequency
CAS Latency = 3
CAS Latency = 2
Access Time from CLK
CAS Latency = 3
CAS Latency = 2
6
9
10
-
ns
ns
125
100
83
-
Mhz
Mhz
8
10
12
-
ns
ns
-8
(1)
-12
(2)
Unit
OPTIONS
• Configurations:
– 32M x 8
– 16M x 16
– 8M x 32
• Power Supply
IS42VMxxx – V
dd
/V
ddq
= 1.8V
• Packages:
x8 –TSOP II (54)
x16 –TSOP II (54), BGA (54)
x32 – TSOP II (86), BGA (90)
• Temperature Range:
Commercial (0°C to +70°C)
Industrial (–40 ºC to 85 ºC)
Notes:
1. Available for x8/x16 only
2. Available for x32 only
ADDRESSING TABLE
Parameter
Configuration
Refresh Count
Row Addressing
Column Addressing
Bank Addressing
Precharge Addressing
32M x 8
8M x 8 x 4 banks
8K/64ms
A0-A12
A0-A9
BA0, BA1
A10
16M x 16
4M x 16 x 4 banks
8K/64ms
A0-A12
A0-A8
BA0, BA1
A10
8M x 32
2M x 32 x 4 banks
4K/64ms
A0-A11
A0-A8
BA0, BA1
A10
Copyright © 2010 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time with-
out notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain
the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be
expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated
Silicon Solution, Inc. receives written assurance to its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
Integrated Silicon Solution, Inc.
- www.issi.com
Rev. A
04/11/2012
1
IS42VM83200D / IS42VM16160D / IS42VM32800D
ISSI’s 256Mb SDRAM is a high speed CMOS, dynamic random-access memory designed to operate in 1.8V V
dd
/
V
ddq
memory systems containing 268,435,456 bits. Internally configured as a quad-bank DRAM with a synchronous
interface. The 256Mb SDRAM includes an AUTO REFRESH MODE, and a power-saving, power-down mode. All
signals are registered on the positive edge of the clock signal, CLK. All inputs and outputs are LVCMOS (VDD =
1.8V) compatible. The 256Mb SDRAM has the ability to synchronously burst data at a high data rate with automatic
column-address generation, the ability to interleave between internal banks to hide precharge time and the capability
to randomly change column addresses on each clock cycle during burst access.
A self-timed row precharge initiated at the end of the burst sequence is available with the AUTO PRECHARGE
function enabled. Precharge one bank while accessing one of the other three banks will hide the precharge cycles
and provide seamless, high-speed, random-access operation. SDRAM read and write accesses are burst oriented
starting at a selected location and continuing for a programmed number of locations in a programmed sequence. The
registration of an Active command begins accesses, followed by a Read or Write command. The ACTIVE command
in conjunction with address bits registered are used to select the bank and row to be accessed (BA0, BA1 select the
bank; A0-A12 (x8 and x16) and A0-A11 (x32) select the row). The READ or WRITE commands in conjunction with
address bits registered are used to select the starting column location for the burst access. Programmable READ or
WRITE burst lengths consist of 1, 2, 4 and 8 locations, or full page, with a burst terminate option.
General Description
FUNCTIONAL BLOCK DIAGRAM (FOR 16M
x
16
BANKS SHOWN)
CLK
CKE
CS
RAS
CAS
WE
DQML
DQMH
16
2
COMMAND
DECODER
&
CLOCK
GENERATOR
DATA IN
BUFFER
16
MODE
REGISTER
13
REFRESH
CONTROLLER
DQ 0-15
SELF
REFRESH
CONTROLLER
A10
A12
A11
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
BA0
BA1
16
DATA OUT
BUFFER
V
DD
/V
DDQ
V
ss
/V
ss
Q
16
REFRESH
COUNTER
8192
8192
8192
8192
ROW DECODER
MULTIPLEXER
13
MEMORY CELL
ARRAY
13
ROW
ADDRESS
LATCH
13
ROW
ADDRESS
BUFFER
BANK 0
SENSE AMP I/O GATE
COLUMN
ADDRESS LATCH
9
512
(x 16)
BANK CONTROL LOGIC
BURST COUNTER
COLUMN
ADDRESS BUFFER
COLUMN DECODER
9
2
Integrated Silicon Solution, Inc.
- www.issi.com
Rev. A
04/11/2012
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