CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Analog Specifications
SYMBOL
R
TOTAL
Over recommended operating conditions unless otherwise stated.
TEST CONDITIONS
W option
U option
MIN
TYP
(NOTE 1)
10
50
-20
V
CC
= 3.3V @ 25°C, wiper current =
V
CC
/R
TOTAL
70
10/10/25
Voltage at pin from GND to V
CC
0.1
1
+20
200
MAX
UNIT
k
k
%
pF
µA
PARAMETER
R
H
to GND resistance
R
H
to GND resistance tolerance
R
W
C
H
/C
L
/C
W
I
LkgDCP
Wiper resistance
Potentiometer capacitance (Note 15)
Leakage on DCP pins (Note 15)
VOLTAGE DIVIDER MODE
(V
CC
@ R
H
i; measured at R
W
i, unloaded; i = 0, 1, 2, or 3)
INL
(Note 6)
DNL
(Note 5)
ZSerror
(Note 3)
FSerror
(Note 4)
V
MATCH
(Note 7)
TC
V
(Note 8)
Integral non-linearity
Differential non-linearity
Zero-scale error
Monotonic over all tap positions
W option
U option
Full-scale error
W option
U option
DCP to DCP matching
Ratiometric temperature coefficient
Any two DCPs at same tap position, same
voltage at all R
H
terminals
DCP register set to 80 hex
-1
-0.5
0
0
-7
-2
-2
±4
1
0.5
-1
-1
1
0.5
7
2
0
0
2
LSB
(Note 2)
LSB
(Note 2)
LSB
(Note 2)
LSB
(Note 2)
LSB
(Note 2)
ppm/°C
RESISTOR MODE
(Measurements between R
W
i and R
H
i. i = 0, 1, 2 or 3)
RINL
(Note 12)
RDNL
(Note 11)
Roffset
(Note 10)
Integral non-linearity
Differential non-linearity
Offset
W option
U option
R
MATCH
(Note 13)
TC
R
(Note 14)
DCP to DCP matching
Resistance temperature coefficient
Any two DCPs at the same tap position with
the same terminal voltages
DCP register set between 20 hex and FF hex
DCP register set between 20 hex and FF
hex; monotonic over all tap positions
-1
-0.5
0
0
-2
±45
1
0.5
1
0.5
7
2
2
MI
(Note 9)
MI
(Note 9)
MI
(Note 9)
MI
(Note 9)
MI
(Note 9)
ppm/°C
FN8094 Rev 1.00
February 8, 2006
Page 3 of 12
ISL90841
Operating Specifications
Over the recommended operating conditions unless otherwise specified.
SYMBOL
I
CC1
I
SB
PARAMETER
V
CC
supply current (volatile
write/read)
V
CC
current (standby)
TEST CONDITIONS
f
SCL
= 400kHz; SDA = Open; (for I
2
C, active,
read and write states)
V
CC
= +5.5V, I
2
C interface in standby state
V
CC
= +3.6V, I
2
C interface in standby state
I
LkgDig
t
DCP
(Note 15)
Leakage current, at pins A0, A1, SDA, Voltage at pin from GND to V
CC
and SCL
DCP wiper response time
SCL falling edge of last bit of DCP data byte
to wiper change
-10
MIN
TYP
(NOTE 1)
MAX
1
5
2
10
1
UNIT
mA
µA
µA
µA
µs
SERIAL INTERFACE SPECS
V
IL
V
IH
Hysteresis
(Note 15)
V
OL
(Note 15)
Cpin
(Note 15)
f
SCL
t
IN
(Note 15)
t
AA
(Note 15)
t
BUF
(Note 15)
t
LOW
t
HIGH
t
SU:STA
t
HD:STA
t
SU:DAT
A1, A0, SDA, and SCL input buffer
LOW voltage
A1, A0, SDA, and SCL input buffer
HIGH voltage
SDA and SCL input buffer hysteresis
SDA output buffer LOW voltage,
sinking 4mA
A1, A0, SDA, and SCL pin
capacitance
SCL frequency
Pulse width suppression time at SDA
and SCL inputs
SCL falling edge to SDA output data
valid
Time the bus must be free before the
start of a new transmission
Clock LOW time
Clock HIGH time
START condition setup time
START condition hold time
Input data setup time
Any pulse narrower than the max spec is
suppressed
SCL falling edge crossing 30% of V
CC
, until
SDA exits the 30% to 70% of V
CC
window
SDA crossing 70% of V
CC
during a STOP
condition, to SDA crossing 70% of V
CC
during the following START condition
Measured at the 30% of V
CC
crossing
Measured at the 70% of V
CC
crossing
SCL rising edge to SDA falling edge; both
crossing 70% of V
CC
From SDA falling edge crossing 30% of V
CC
to SCL falling edge crossing 70% of V
CC
From SDA exiting the 30% to 70% of V
CC
window, to SCL rising edge crossing 30% of
V
CC
From SCL rising edge crossing 70% of V
CC
to SDA entering the 30% to 70% of V
CC
window
From SCL rising edge crossing 70% of V
CC
,
to SDA rising edge crossing 30% of V
CC
From SDA rising edge to SCL falling edge;
both crossing 70% of V
CC
From SCL falling edge crossing 30% of V
CC
,
until SDA enters the 30% to 70% of V
CC
window
From 30% to 70% of V
CC
1300
-0.3
0.7*V
CC
0.05*
V
CC
0
0.4
10
400
50
900
0.3*V
CC
V
CC
+0.3
V
V
V
V
pF
kHz
ns
ns
ns
1300
600
600
600
100
ns
ns
ns
ns
ns
t
HD:DAT
Input data hold time
0
ns
t
SU:STO
t
HD:STO
t
DH
(Note 15)
t
R
(Note 15)
STOP condition setup time
STOP condition hold time for read, or
volatile only write
Output data hold time
600
600
0
ns
ns
ns
SDA and SCL rise time
20 +
0.1 * Cb
250
ns
FN8094 Rev 1.00
February 8, 2006
Page 4 of 12
ISL90841
Operating Specifications
Over the recommended operating conditions unless otherwise specified.
(Continued)
SYMBOL
t
F
(Note 15)
Cb
(Note 15)
Rpu
(Note 15)
t
SU:A
t
HD:A
PARAMETER
SDA and SCL fall time
Capacitive loading of SDA or SCL
TEST CONDITIONS
From 70% to 30% of V
CC
Total on-chip and off-chip
MIN
20 +
0.1 * Cb
10
1
TYP
(NOTE 1)
MAX
250
400
UNIT
ns
pF
k
SDA and SCL bus pull-up resistor off- Maximum is determined by t
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