CHPHT
www.vishay.com
Vishay Sfernice
High Temperature (245 °C) Thick Film Chip Resistor
FEATURES
• High temperature (245 °C)
• Large ohmic value range 0.1
to 100 M
• Operating temperature range
(-55 °C to +230 °C)
• SMD wraparound chip resistor
• Storage temperature range
(-55 °C to +245 °C)
Available
DESIGN SUPPORT TOOLS
Models
Available
click logo to get started
• Gold terminations for HMP process (< 1 μm thick) for
temperature up to 245 °C
• Tin / silver terminations for operating temperature up to
200 °C
• Material categorization: for definitions of compliance
please see
www.vishay.com/doc?99912
For applications such as down hole applications or aircraft breaking systems, the need for parts able to withstand very severe
conditions (temperature as high as 230 °C powered or up to 245 °C un-powered) has leaded Vishay Sfernice to push out the
limit of the thick film technology. Designers might read the application note “Power Dissipation Considerations in High Precision
Vishay Sfernice Thin Film Chips Resistors and Arrays (P, PRA etc.) (High Temperature Applications)”
(www.vishay.com/doc?53047) in conjunction with this data sheet to help them to properly design their PCBs and get the best
performances of the CHPHT. Vishay Sfernice R&D engineers will be willing to support any customer design considerations.
DIMENSIONS
in millimeters
D
C
B
E
A
CASE SIZE
0603
0805
1206
2010
A
± 0.152
1.60
1.85
3.00
5.03
B
± 0.127
0.90
1.25
1.73
2.64
C
± 0.127
0.38
0.38
0.38
0.50
D
± 0.127
0.31
0.31
0.40
0.50
E
± 0.127
0.40
0.50
0.50
0.50
SUGGESTED LAND PATTERN
(to IPC-7351A)
G
min.
X
max.
Z
max.
CASE SIZE
0603
0805
1206
2010
Revision: 24-Jan-18
Z
max.
2.15
2.70
3.85
5.88
G
min.
0.39
0.44
1.59
3.62
X
max.
1.03
1.38
1.85
2.77
Document Number: 52032
1
For technical questions, contact:
sferthinfilm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT
www.vishay.com/doc?91000
CHPHT
www.vishay.com
Vishay Sfernice
RATED
POWER
Pn
W
(at 230 °C)
0.0125
0.02
0.025
0.1
STANDARD ELECTRICAL SPECIFICATIONS
MODEL
SIZE
RESISTANCE
RANGE
0.1 to 25M
0.1 to 25M
0.1 to 50M
0.1 to 100M
LIMITING
ELEMENT
VOLTAGE
V
50
150
200
200
MAX.
OVERLOAD
VOLTAGE
V
100
300
400
400
TOLERANCE
±%
TEMPERATURE
COEFFICIENT
± ppm/°C
100, 200
100, 200
100, 200
100, 200
CHPHT
CHPHT
CHPHT
CHPHT
0603
0805
1206
2010
1, 2, 5
1, 2, 5
1, 2, 5
1, 2, 5
CLIMATIC SPECIFICATIONS
Operating temperature range
Storage temperature range
-55 °C to +230 °C
-55 °C to +245 °C
PACKAGING
ESD packaging available: Waffle pack and plastic tape and
reel (low conductivity). Paper tapes available on request
(ESD only). (For 0603, 0805, and 1206 only.)
NUMBER OF PIECESPER PACKAGE
SIZE
WAFFLE
PACK
TAPE AND REEL
MIN.
MAX.
5000
100
0805
100
1206
2010
140
60
2000
4000
8 mm
TAPE
WIDTH
MECHANICAL SPECIFICATIONS
Substrate
Technology
Protection
Alumina
Thick film (Ruthenium oxyde)
0.5
<
R
< 100 M:
double organic coating
R
0.5
:
overglaze protection
(no organic coating)
N (W/A):
SnAg over nickel
barrier for temperature
up to 200 °C
G (W/A) type:
Gold (< 1 μm) over
nickel barrier for temperature
up to 245 °C
0603
Terminations
PACKAGING RULES
Waffle Pack
Can be filled up to maximum quantity indicated in the table
here above, taking into account the minimum order quantity.
When quantity ordered exceeds maximum quantity of a
single waffle pack, the waffle packs are stacked up on the
top of each other and closed by one single cover.
To get “not stacked up” waffle pack in case of ordered
quantity > maximum number of pieces per package:
Please consult Vishay Sfernice for specific ordering
code
Tape and Reel
Can be filled up to maximum quantity indicated in the table
here above, taking into account the minimum order quantity.
When quantity ordered is between the MOQ and the
maximum reel capacity, only one reel is provided.
When several reels are needed for ordered quantity
within MOQ and maximum reel capacity: Please consult
Vishay Sfernice for specific ordering code
Note
• Refer to Application Note “Guidelines for Vishay Sfernice
Resistive and Inductive Components” (document number:
52029) for recommended reflow profile. Profile #3 applies
BEST TOL. AND TCR VERSUS OHMIC VALUE
TIGHTEST
TOLERANCE
1 % (F)
2 % (G)
5 % (J)
OHMIC
VALUES
5
<
R
< 10M
1
<
R
<
R
max.
0.1
<
R
<
R
max.
BEST TCR
ppm/°C
100 (K)
200 (L)
200 (L)
POWER DERATING CURVE
Rated Power (%)
1200
1000
800
600
400
200
0
0
50
100
150
200
250
300
Ambient Temperature in °C
Revision: 24-Jan-18
Document Number: 52032
2
For technical questions, contact:
sferthinfilm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT
www.vishay.com/doc?91000
CHPHT
www.vishay.com
POPULAR OPTIONS
For any option it is recommended to consult Vishay Sfernice for availability first.
Option: Enlarged terminations:
For stringent and special power dissipation requirements, the thermal resistance between the resistive layer and the solder joint
can be reduced using enlarged terminations chip resistors which are soldered on large and thick copper pads acting as heat
sinks (see application note: “Power Dissipation in High Precision Vishay Sfernice Chip Resistors and Arrays (P Thin Film, PRA
Arrays, CHP Thick Film” (www.vishay.com/doc?53048).
Option to order: 0063 (applies to size 1206/2010).
Vishay Sfernice
DIMENSIONS
(Option 0063) in millimeters
Bottom view for mounting
A
Uncoated
ceramic
Enlarged
termination
B
F
D
E
A
CASE
SIZE
MAX. TOL.
+0.152
MIN. TOL.
-0.152
NOMINAL
1206
2010
3.06 (0.120)
5.08 (0.200)
B
MAX. TOL.
+0.127
MIN. TOL.
-0.127
NOMINAL
1.60 (0.063)
2.54 (0.100)
E
MAX. TOL.
+0.13
MIN. TOL.
-0.13
NOMINAL
0.40 (0.016)
0.48 (0.019)
D
MAX. TOL.
+0.13
MIN. TOL.
-0.13
NOMINAL
1.22 (0.048)
2.23 (0.088)
NOMINAL
0.63 (0.024)
0.63 (0.024)
F
MIN.
0.50 (0.020)
0.50 (0.020)
MAX.
0.76 (0.030)
0.76 (0.030)
SUGGESTED LAND PATTERN
(Option 0063)
G
min.
X
max.
Z
max.
DIMENSIONS (in millimeters)
CHIP SIZE
Z
max.
1206
2010
3.91 (0.154)
5.93 (0.233)
G
min.
0.50 (0.020)
0.50 (0.020)
X
max.
1.73 (0.068)
2.67 (0.105)
Revision: 24-Jan-18
Document Number: 52032
3
For technical questions, contact:
sferthinfilm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT
www.vishay.com/doc?91000
CHPHT
www.vishay.com
Vishay Sfernice
TYPICAL VALUES
AND DRIFTS
< ± 0.1 %
< ± 0.1 %
< ± 0.1 %
PERFORMANCE
TESTS
Termination adhesion
Resistance to solder heat
Rapid temperature change
CONDITIONS
5N for 10 s
Immersion 10 s
in Sn/Pb 60/40
at +260 °C
5 cycles
-55 °C to +155 °C
Phase A dry heat
Phase B damp heat
Phase C cold -55 °C
Phase D damp heat 5 cycles
56 days
AEC-Q200
85 °C / 85 % RH / Pn
1000 h
6.25 Pn
for 2 s
1000 h at rated power
at 230 °C
1000 h at 245 °C
REQUIREMENTS
± (0.25 % + 0.05
)
± (0.25 % + 0.05
)
± (0.25 % + 0.05
)
Climatic sequence
Humidity (steady state)
Moisture resistance
Short time overload
Load life
Shelf life
± (1 % + 0.05
)
± (1 % + 0.05
)
3 % + 0.05
± (0.25 % + 0.05
)
-
-
< ± 0.2 %
< ± 0.2 %
Max. < 3 % + 0.05
< ± 0.1 %
1 % max.
1 % max.
GLOBAL PART NUMBER INFORMATION
Global Part Numbering: CHPHT0805K1001FGT
C
GLOBAL
MODEL
CHPHT
H
P
H
T
0
8
0
5
K
1
0
0
1
F
G
T
SIZE
0603
0805
1206
2010
TCR
K
= 100 ppm
L
= 200 ppm
VALUE
The first 3 digits
are significant
figures and the
last digit specifies
the number of
zeros to follow.
R designates
decimal point
10R0 = 10
3901 = 3900
1004 = 1 M
TOLERANCE
F
=±1%
G
=±2%
J
=±5%
TERMINATION
(1)
N:
SnAg over nickel barrier
G:
gold over nickel barrier
PACKAGING
For more
information see
“Codification of
packaging”
table
OPTION
Leave blank
if no option
Note
(1)
N terminations for temperature up to 200 °C
G terminations for temperature up to 230 °C
Revision: 24-Jan-18
Document Number: 52032
4
For technical questions, contact:
sferthinfilm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT
www.vishay.com/doc?91000
CHPHT
www.vishay.com
Vishay Sfernice
CODIFICATION OF PACKAGING
WAFFLE PACK
W
WA
PLASTIC TAPE (Standard for all sizes)
T
TA
TB
TC
TD
TE
TF
PT
PA
PB
PC
PD
PE
PF
100 min., 1 mult
100 min., 100 mult
250 min., 250 mult
500 min., 500 mult
1000 min., 1000 mult
2500min., 2500 mult
Full tape (quantity depending on size of chips)
100 min., 1 mult
100 min., 100 mult
250 min., 250 mult
500 min., 500 mult
1000 min., 1000 mult
2500min., 2500 mult
Full tape (quantity depending on size of chips)
100 min., 1 mult
100 min., 100 mult (available only in size 1206)
PAPER TAPE (Available for 0603, 0805, and 1206. Please consult Vishay Sfernice for other sizes)
CODIFICATION OF OPTIONS ON TWO DIGITS
OPTION
..
0099
0100
0101
0102
0103
0104
0105
..
0124
0125
OPTION 2
DIGITS
..
99
0A
0B
0C
0D
0E
0F
..
0Y
0Z
OPTION
0126
0127
0128
..
0320
0321
0322
0323
0324
0325
..
OPTION 2
DIGITS
1A
1B
1C
..
8M
8N
8O
8P
8Q
8R
..
CODIFICATION OF SIZES
CODE 18
7
8
9
A
B
C
D
E
F
G
H
I
J
K
L
CODE 40
02016
0302
0402
0502
0505
0603
0805
1005
1010
1020
1206
1505
2010
2208
2512
CODE 18
M
N
O
P
Q
R
S
T
U
V
W
X
Y
Z
CODE 40
22
33
44
55
515
48
408
816
914
073
074
100
135
182
Revision: 24-Jan-18
Document Number: 52032
5
For technical questions, contact:
sferthinfilm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT
www.vishay.com/doc?91000
FPGA/CPLD
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
