USER’S MANUAL
HIP6302EVAL1
Multiphase Power Conversion for AMD Athlon Processors up to 35A
AN9888
Rev.1.00
February 2002
Introduction
Each generation of computer microprocessor brings
performance advances in computing power. Performance
improvements are made possible by advances in fabrication
technology that enable greater device density. Newer
processors are operating at lower voltages and higher clock
speeds both of which contribute to greater demands on the
microprocessor core voltage supply in terms of higher peak
currents and higher current-slew rates.
Intersil’s family of multi-phase DC-DC converter solutions
provide the ideal solution to supply the core-voltage needs of
present and future high-performance microprocessors.
protection. A five-bit DAC provides a digital interface to
program the 1% accurate reference and a window
comparator toggles PGOOD if the output voltage is out of
range and acts to protect the load in case of over voltage.
For more detailed descriptions of the HIP6302 functionality,
refer to the HIP6302 Data Sheet [1].
The HIP6601A is a driver IC capable of delivering up to 2A of
gate-charging current for rapidly switching both MOSFETs in
a synchronous-rectified bridge. The HIP6601A accepts a
single logic input to control both upper and lower MOSFETs.
Adaptive shoot-through protection is provided on both
switching edges to provide optimal dead time, and bootstrap
circuitry permits greater enhancement of the upper
MOSFET. For a more detailed description of the HIP6601A,
refer to the HIP6601A Data Sheet [2].
Intersil HIP6302 and HIP6601
The HIP6302 controller IC works with two HIP6601A or
HIP6603A single-channel driver ICs or a single HIP6602A
dual-channel driver IC [3] to form a highly integrated solution
for high-current, high slew-rate applications. The HIP6302
regulates output voltage, balances load currents and
provides protective functions for two synchronous-rectified
buck-converter channels.
PGOOD
15
VSEN
UV
+
-
OV
LATCH
OVP
+
-
S
VCC
16
POWER-ON
RESET (POR)
THREE STATE
CLOCK AND
SAWTOOTH
GENERATOR
8
FS/DIS
PVCC
VCC
7
6
+5V
2 BOOT
1 UGATE
PWM
3
10k
CONTROL
LOGIC
SHOOT
THROUGH
PROTECTION
8 PHASE
10k
10
x 0.9
5 LGATE
4
GND
x 1.15
FIGURE 2. HIP6601A BLOCK DIAGRAM
SOFT START
AND FAULT
LOGIC
COMP
VID4
VID3
VID2
VID1
VID0
6
1
2
3
4
5
+
-
PWM
+
+
-
PWM
13 PWM1
The HIP6302EVAL1 Board and Reference
Design
With the VID jumpers set to 1.7V (00110), the evaluation
board meets the output voltage and current specifications
indicated in Table 1.
TABLE 1. HIP6302EVAL1 OUTPUT PARAMETERS
DAC
+
-
E/A
-
+
-
12 PWM2
FB 7
CURRENT
DETECTION
MIN
14 ISEN1
11 ISEN2
MAX
1.75V
1.85V
2.00V
35A
57A
35A/s
Static Regulation
Transient Regulation
Over-Voltage Protection
Continuous Load Current
Over-Current Trip Level
Load-Current Transient
1.65V
1.60V
1.90V
-
41A
-
+
9
GND
+
FIGURE 1. HIP6302 BLOCK DIAGRAM
The integrated high-bandwidth error amplifier provides
voltage regulation, while current-sense circuitry maintains
phase-current balance between the two power channels and
provides feedback for droop compensation and over-current
AN9888 Rev.1.00
February 2002
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HIP6302EVAL1
The HIP6302EVAL1 evaluation board incorporates a reference
design intended to meet the core-voltage requirements for
AMD Athlon microprocessors up to 35A. Additional circuitry
is provided to facilitate circuit evaluation including input and
output power connectors, VID jumpers, numerous probe
points, an LED power-good indicator, and a load-transient
generator.
Start Up
The waveforms in Figure 3 demonstrate the normal start-up
sequence with the HIP6302EVAL1 connected to a 55m load.
After FS/EN is released, VCORE exhibits a linear ramp until
reaching its 1.7V set point. The gradual increase of VCORE
over approximately 5ms limits the current required from the
input supply, ICC5, to a level that does not strain the supply.
The HIP6302 asserts PGOOD once VCORE is within
regulation limits.
Powering the HIP6302EVAL1
For convenience, the HIP6302EVAL1 provides two methods of
making input power connections. The 20-pin header, J1,
interfaces with a standard ATX power supply and may be the
most convenient method of powering the board.
J2, J3, and J4 are standard banana-jack connectors that can
be used to supply power using bench-top power supplies.
These inputs provide greater versatility in testing and design
validation by allowing the 12V and 5V power-input voltage
levels to be varied independently. In this way power-on level
and power-sequencing issues can be easily examined.
To start the evaluation board, insert the 20-pin connector from
an ATX supply into J1. If using bench-top supplies, connect a
12V supply to J2 and a 5V supply to J3. Connect the grounds
from both supplies to J4.
FS/EN, 5V/DIV
0V
VCORE, 1V/DIV
0V
ICC5, 10A/DIV
0A
PGOOD, 5V/DIV
0V
1ms/DIV
Important
There are two things to consider when using bench-top
supplies. If the 5V supply is applied prior to the 12V supply, the
HIP6302 will begin operating before the HIP6601As. This
allows the HIP6302 to complete its soft-start cycle before the
drivers are capable of switching power to the output. When the
12V power input is then applied, there is a large transient as
the controller tries to instantly bring the output to its full-voltage
level. This can result in an overcurrent protection cycle and an
abnormal start-up waveform. It can be avoided by applying 5V
supply after or at the same time as the 12V supply or by using
an ATX power supply.
The second problem can occur when operating the transient
load generator. Not all bench-top and ATX power supplies are
capable of responding to load transients, and they may allow a
momentary voltage dip on VCC5. This can activate the power-
on-reset function in the HIP6302 and cause the output power
to cycle. It can be remedied by connecting a 5600F or larger
capacitor between VCC5 and ground. The capacitor, if
necessary, simulates the distributed capacitance that exists on
the computer motherboard.
FIGURE 3. HIP6302EVAL1 START-UP WAVEFORMS
Transient Response
The HIP6302EVAL1 is equipped with a load-transient
generator that applies a 0–36A transient load current with rise
and fall rates of approximately 35A/s. The duration of the
transient is between 100s and 200s, and the repetition rate
is kept low in order to limit power dissipation in the load
MOSFETs and resistors. Removal of the HI/LO jumper (JP2)
causes the current to decrease from about 36A to about 31A.
The load-transient generator operates when the
HIP6302EVAL1 is properly connected to a 12V power source
and SW1 is in the ON position. Operation ceases when SW1 is
moved into the OFF position or 12V is removed from the
board.
The HIP6302EVAL1 achieves the specified transient
performance while maintaining a favorable balance between
low cost, high efficiency and small profile. When the duty cycle
changes rapidly in response to a transient load current, the
inductor current immediately begins to change in order to meet
the demand. During the time the inductor current is increasing,
the output-filter capacitors are supplying the load. It follows that
the amount of required capacitance decreases as the
capability of the inductors to rapidly assume the load current
increases.
AN9888 Rev.1.00
February 2002
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HIP6302EVAL1
Figure 4 shows the core voltage, inductor current, and PWM
signals changing in response to the transient load current. The
upper waveform shows the core voltage deviating from its no-
load setting of 1.72V to a minimum of about 1.62V upon the
application of current. The voltage then settles to its 1.67V full-
load setting. On load removal, the core voltage peaks at a level
of 1.78V before settling again to its 1.72V no-load setting.
Although the specified operating range allows deviations as
low as 1.60V and as high as 1.85V, a minimum of 20mV is
reserved to allow for the reference tolerance and the
tolerances of other components that contribute to the overall
system accuracy.
The close up in Figure 6 shows the core-voltage, inductor-
current and PWM signals changing in response to the trailing
edge of the transient load current. Again, the duty cycles
immediately decrease to zero, and the inductors begin
shedding load current at the maximum rate. Note that the
inductor currents briefly go negative as the transient settles.
The capacitors are slightly over charged at the end of the
transient, and the discharge path is in the reverse direction
through the inductors.
CORE VOLTAGE,
50mV/DIV
1.7V
CORE VOLTAGE, 50mV/DIV
1.7V
INDUCTOR CURRENTS,
10A/DIV
INDUCTOR CURRENTS, 10A/DIV
0A
0V
0A
0V
0V
0V
PWM1, 10V/DIV
PWM2, 10V/DIV
5s/DIV
PWM1, 10V/DIV
PWM2, 10V/DIV
20s/DIV
FIGURE 6. TRANSIENT-RESPONSE TRAILING EDGE
Overcurrent Protection
When the current out of either ISEN pin exceeds 82A, the
HIP6302 detects an overcurrent condition and responds by
placing the PWM outputs into a high-impedance state. This
signals the HIP6601 to turn off both upper and lower MOSFETs
in order to remedy the overcurrent condition.This behavior is
seen in Figure 7 where PWM1 goes immediately to 2.5VDC when
the output current reaches approximately 50A. The output voltage
then quickly falls to zero.
FIGURE 4. HIP6302EVAL1 TRANSIENT RESPONSE
Figure 5 is a close-up showing the core-voltage, inductor-
current and PWM signals responding at the leading edge of the
transient load
current. The PWM signals increase to their
maximum duty cycle of 75% on the first pulse following the
start of the transient. The inductor currents begin to increase
immediately and are carrying all of the load within 10s. The
very fast transient response is due to the precision 18MHz
error amplifier and optimal compensation of the control loop.
1.7V
CORE VOLTAGE, 50mV/DIV
INDUCTOR CURRENTS,
10A/DIV
0V
OUTPUT CURRENT,
20A/DIV
0A
CORE VOLTAGE,
500mV/DIV
PWM1, 5V/DIV
0A
0V
0V
PWM1, 10V/DIV
PWM2, 10V/DIV
5s/DIV
0V
50s/DIV
FIGURE 7. OVERCURRENT BEHAVIOR
FIGURE 5. TRANSIENT-RESPONSE LEADING EDGE
AN9888 Rev.1.00
February 2002
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HIP6302EVAL1
After the initial over-current trip, the HIP6302 waits for a period
of time equal to 2048/f
SW
(f
SW
is the switching frequency)
before initiating a soft-start cycle. If the over-load condition
remains, another over-current trip will occur before the end of
the soft-start sequence. This repetitive over-current cycling is
illustrated in Figure 8, and will continue indefinitely unless the
fault is cleared or power to the converter is removed. Because
of the wait period, the worst case power delivered during
overcurrent cycling is equal to 45% of the power delivered
during normal operation at full load. Therefore, indefinite over-
current cycling does not create a thermal problem for the
circuit.
Summary
The HIP6302EVAL1 is intended to provide a convenient
platform to evaluate the performance of the HIP6302 -
HIP6601A chip set in the specific implementation indicated in
Table 1. The design demonstrates a favorable trade off
between low cost, high efficiency, and small footprint. The
following pages include schematic, bill of materials, and layout
drawings to facilitate implementation of this solution. The
evaluation board is simple and convenient to operate, and test
points are available to evaluate the most commonly tested
parameters. Example waveforms are given for reference.
The HIP6302 and HIP6601A provide a versatile 2-phase
power solution for low-voltage applications from 25A to
approximately 40A, and together they result in the most
effective solution available.
OUTPUT CURRENT, 20A/DIV
References
0A
CORE VOLTAGE,
500mV/DIV
For Intersil documents available on the internet, see web site
http://www.intersil.com/
Intersil Technical Support 1 (888) INTERSIL
[1]
HIP6302 Data Sheet,
Intersil Corporation, Power
Management Products Division, 2000.
(http://www.intersil.com/).
[2]
HIP6601A, HIP6603A Data Sheet,
Intersil Corporation,
Power Management Products Division, 2000.
[3]
HIP6602A Data Sheet,
Intersil Corporation, Power
Management Products Division, 2000.
0V
5ms/DIV
FIGURE 8. OVERCURRENT BEHAVIOR
Efficiency
Figure 9 shows the efficiency versus current plot for the
HIP6302EVAL1 for 5A through 35A. The measurements were
made at room temperature with natural convection cooling
only..
90
85
EFFICIENCY (%)
80
75
70
5
10
15
20
25
30
35
CURRENT (AMPERES)
FIGURE 9. EFFICIENCY vs CURRENT
AN9888 Rev.1.00
February 2002
Page 4 of 12
HIP6302EVAL1
Schematic
5VIN
12VIN
16
C7
0.1F
9
C6
1F
6
VCC
GND
PWM1
13
TP3
JP1
1
2
3
4
5
VID4
VID3
VID2
VID1
VID0
C12
1F
C8
0.1F
Q3
HUF76139
L3
450nH
ISEN1
14
R1
2.15k
3
7
VCC
PVCC
2
L1
1F
C3
0.1F
C4
1F
Q1
HUF76139
L2
450nH
C5
100F
C1
1000F
BOOT 1
UGATE
8
5
PWM PHASE
HIP6601
LGATE
GND
4 U1
Q2
HUF76139
TP2
TP1
C9
1F
C10
100F
C2
1000F
HIP6302
6
7 2
VCC
PVCC
BOOT 1
UGATE
8
15
PGOOD
PWM2
12
TP4
3
PWM PHASE
HIP6601
LGATE 5
GND
Q4
HUF76139
TP6
4 U3
FS/DIS
R3
107k
COMP
6
FB
7
R4
14.0k
TP7
C11
2.2nF
R6
45.3k
ISEN2
VSEN
10
R5
1.00k
11
R2
2.15k
TP5
C13-C17
22F
C18-C21
560F
JP2
C48
1F
Q7
HUF76129
R8
10k
R7
1k
RED
R9
1k
GREEN
CR1
Q5
2N7002
R15
0.200
Q6
HUF76129
TP11
R17
46.4k
R18
400
Q8
2N7002
C49
10F
4
7
1
VDD
2
HB
6
LI
HO
3
LO
HI
8
SW1
ON
OFF
U4
HIP2100
HS
VSS
R14, R16
0.100
POWER GOOD INDICATOR
R10
D1
BAV99
1.50k
R11
619
R12
D2
BAV99
1.50k
R13
619
TRANSIENT GENERATOR
AN9888 Rev.1.00
February 2002
Page 5 of 12
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