S i 3 2 2 0 /2 5
S i 3 2 0 0 /0 2
D
U A L
P
RO
SLIC
®
P
ROGRAMMABLE
CMOS SLIC/C
ODEC
Features
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Si3220
Si3225
Performs all BORSCHT functions
Ideal for applications up to 18 kft
Internal balanced and unbalanced ringing
(Si3220)
External bulk ringer support (Si3225)
Software-programmable parameters:
Ringing frequency, amplitude, cadence,
and waveshape (Si3220)
Two-wire ac impedance
Transhybrid balance
DC current loop feed
Loop closure and ring trip thresholds
Ground key detect threshold
Automatic switching of up to three battery
supplies
On-hook transmission
Loop or ground start operation with
smooth/abrupt polarity reversal
Modem/fax tone detection
DTMF generation/decoding
Dual tone generators
A-Law/µ-Law, linear PCM
companding
PCM and SPI bus digital interfaces
with programmable interrupts
GCI mode support
3.3 or 5 V operation
GR-909 loop diagnostics
Audio diagnostics with loopback
12 kHz/16 kHz pulse metering
(Si3220)
FSK caller ID generation
Lead-free/RoHS-compliant
Part Number
Ringing
Method
Internal
External
Ringer
Applications
Ordering Information
Digital loop carriers
Central Office telephony
Pair gain remote terminals
Wireless local loop
Private Branch Exchange (PBX) systems
Cable telephony
Voice over IP/voice over DSL
ISDN terminal adapters
See “Dual ProSLIC Selection
Guide” on page 110.
Description
U.S. Patent #6,567,521
U.S. Patent #6,812,744
Other patents pending
The Dual ProSLIC
®
is a series of low-voltage CMOS devices that integrate both
SLIC and codec functionality into a single IC to provide a complete dual-channel
analog telephone interface in accordance with all relevant LSSGR, ITU, and ETSI
specifications. The Si3220 includes internal ringing generation to eliminate
centralized ringers and ringing relays, and the Si3225 supports centralized ringing
for long loop and legacy applications. On-chip subscriber loop and audio testing
allows remote diagnostics and fault detection with no external test equipment or
relays. The Si3220 and Si3225 operate from a single 3.3 or 5 V supply and
interface to standard PCM/SPI or GCI bus digital interfaces. The Si3200/2 linefeed
ICs perform all high-voltage functions and operate from a 3.3 or 5 V supply as well
as single or dual battery supplies up to 100 V (Si3200) or 125 V (Si3202). The
Si3220 and Si3225 are available in a 64-pin thin quad flat package (TQFP), and the
Si3200/2 is available in a thermally-enhanced 16-pin small outline (SOIC) package.
Functional Block Diagram
INT RESET
Si3220/25
CS
SCLK
SDO
SDI
Ringing
Generator
& Ring Trip
Sense
SPI
Control
Interface
Pulse Metering
Subscriber Line
Diagnostics
2-Wire AC
Impedance
Hybrid Balance
DTMF Decode
FSK
text
Caller ID
Codec A
SLIC A
Linefeed
Control
Si3200/2
TIP
Linefeed
Interface
Channel A
RING
DAC
ADC
Linefeed
Monitor
DTX
DRX
FSYNC
DSP
PCM /
GCI
Interface
Codec B
Dual Tone
Generators
Modem Tone
Detection
Gain Adjust
SLIC B
Linefeed
Control
Si3200/2
TIP
Linefeed
Interface
Channel B
RING
DAC
Loop Closure,
& Ground Key
Detection
PCLK
PLL
Programmable
Audio Filters
ADC
Relay Drivers
Linefeed
Monitor
Rev. 1.3 6/06
Copyright © 2006 by Silicon Laboratories
Si3220/25 Si3200/02
2
Si3220/25 Si3200/02
Rev. 1.3
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Si3220/25 Si3200/02
T
ABLE O F
C
ONTENTS
Section
Page
1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
2. Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.1. Dual ProSLIC Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.2. Power Supply Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3.3. DC Feed Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3.4. Adaptive Linefeed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
3.5. Ground Start Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
3.6. Linefeed Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
3.7. Loop Voltage and Current Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
3.8. Power Monitoring and Power Fault Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
3.9. Automatic Dual Battery Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
3.10. Loop Closure Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
3.11. Ground Key Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
3.12. Ringing Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
3.13. Internal Unbalanced Ringing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
3.14. Ringing Coefficients . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
3.15. Ring Trip Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
3.16. Relay Driver Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
3.17. Polarity Reversal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
3.18. Two-Wire Impedance Synthesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
3.19. Transhybrid Balance Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
3.20. Tone Generators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
3.21. Caller ID Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
3.22. Pulse Metering Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
3.23. DTMF Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
3.24. Modem Tone Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
3.25. Audio Path Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
3.26. System Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
3.27. Interrupt Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
3.28. SPI Control Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
3.29. PCM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
3.30. PCM Companding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
3.31. General Circuit Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
3.32. System Testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
4. Pin Descriptions: Si3220/25 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
5. Pin Descriptions: Si3200/2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
6. Package Outline: 64-Pin TQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107
7. Package Outline: 16-Pin ESOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
8. Silicon Labs Si3220/25 Support Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
9. Dual ProSLIC Selection Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110
Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112
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Rev. 1.3
3
Si3220/25 Si3200/02
1. Electrical Specifications
Table 1. Absolute Maximum Ratings and Thermal Information
1
Parameter
Si3220/Si3225
Supply Voltage
STIPAC, STIPDC, SRINGAC, SRINGDC Current
Input Current, Digital Pins
Input Voltage, Digital Pins
I
IN
V
DD1-
V
DD4
–0.5
–20
–10
6.0
+20
+10
V
DDD
+0.3
+50
+50
V
mA
mA
V
mV
mV
Symbol
Test Condition
Min
Max
Unit
Analog Ground Differential Voltage
(GND1 to ePad, GND2 to ePad or GND1 to GND2)
2
Digital Ground Differential Voltage
(GND3 to GND4)
2
Si3200
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V
IND
–0.3
–50
–50
V
GNDA
V
GNDD
V
DD
–0.5
V
BATH
Continuous
10 ms
–104
–109
V
BAT
,
V
BATL
Continuous
Continuous
V
BATH
–104
V
TIP
,
V
RING
Pulse < 10 us
Pulse < 4 us
I
TIP
, I
RING
–100
V
DD
–0.5
Rev. 1.3
Supply Voltage
6.0
0.4
0.4
0.4
0.4
0.4
0.4
+100
V
V
V
V
V
V
V
mA
High Battery Supply Voltage
3
Low Battery Supply Voltage
TIP or RING Voltage
V
BATH
–15
V
BATH
–35
TIP or RING Current
Si3202
Supply Voltage
6.0
V
Notes:
1.
Permanent device damage may occur if the absolute maximum ratings are exceeded, and exposure to absolute
maximum rating conditions for extended periods may affect device reliability. Functional operation should be restricted
to the conditions as specified in the operational sections of this data sheet.
2.
The PCB pad placed under the device package must be connected with multiple vias to the PCB ground layer and to
the GND1-GND4 pins via short traces. The TQFP-64 e-Pad must be properly soldered to the PCB pad during PCB
assembly. This type of low-impedance grounding arrangement is necessary to ensure that maximum differentials are
not exceeded under any operating condition in addition to providing thermal dissipation.
3.
On Si3200 revision E, the dv/dt of the voltage applied to the V
BAT
, V
BATH
, and V
BATL
pins must be limited to 10 V/µs.
4.
Operation of the Si3220/Si3225 above 125
C
junction temperature may degrade device reliability. The Si3200/Si3202
should be operated at a junction temperature below 140
C
for optimal reliability.
5.
The thermal resistance of an exposed pad package is assured when the recommended printed circuit board layout
guidelines are followed correctly. The specified performance requires that the exposed pad be soldered to an exposed
copper surface of equal size and that multiple vias are added to enable heat transfer between the top-side copper
surface and a large internal copper ground plane. Refer to “AN55: Dual ProSLIC
®
User Guide” or to the Si3220/3225
evaluation board data sheet for specific layout examples.
4
Si3220/25 Si3200/02
Table 1. Absolute Maximum Ratings and Thermal Information
1
(Continued)
Parameter
High Battery Supply Voltage
Symbol
V
BATH
Test Condition
Continuous
10 ms
Low Battery Supply Voltage
TIP or RING Voltage
V
BAT
,
V
BATL
V
TIP
,
V
RING
Continuous
Continuous
Pulse < 10 us
Pulse < 4 us
Min
–130
–135
V
BATH
–130
V
BATH
–15
V
BATH
–35
–100
Max
0.4
0.4
0.4
0.4
0.4
0.4
+100
Unit
V
V
V
V
V
V
mA
TIP or RING Current
Thermal Information
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I
TIP
, I
RING
–40
–40
JA
JA
TQFP-64 ePad
SOIC-16 ePad
Rev. 1.3
Operating temperature (All devices)
4
Storage temperature (All devices)
+100
+150
C
C
C/W
C/W
Thermal Resistance (Si3220/Si3225)
5
Thermal Resistance (Si3200/Si3202)
5
25 (typical)
55 (typical)
Notes:
1.
Permanent device damage may occur if the absolute maximum ratings are exceeded, and exposure to absolute
maximum rating conditions for extended periods may affect device reliability. Functional operation should be restricted
to the conditions as specified in the operational sections of this data sheet.
2.
The PCB pad placed under the device package must be connected with multiple vias to the PCB ground layer and to
the GND1-GND4 pins via short traces. The TQFP-64 e-Pad must be properly soldered to the PCB pad during PCB
assembly. This type of low-impedance grounding arrangement is necessary to ensure that maximum differentials are
not exceeded under any operating condition in addition to providing thermal dissipation.
3.
On Si3200 revision E, the dv/dt of the voltage applied to the V
BAT
, V
BATH
, and V
BATL
pins must be limited to 10 V/µs.
4.
Operation of the Si3220/Si3225 above 125
C
junction temperature may degrade device reliability. The Si3200/Si3202
should be operated at a junction temperature below 140
C
for optimal reliability.
5.
The thermal resistance of an exposed pad package is assured when the recommended printed circuit board layout
guidelines are followed correctly. The specified performance requires that the exposed pad be soldered to an exposed
copper surface of equal size and that multiple vias are added to enable heat transfer between the top-side copper
surface and a large internal copper ground plane. Refer to “AN55: Dual ProSLIC
®
User Guide” or to the Si3220/3225
evaluation board data sheet for specific layout examples.
5
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