DATASHEET
ISL6539
Wide Input Range Dual PWM Controller with DDR Option
The ISL6539 dual PWM controller delivers high efficiency and
tight regulation from two voltage regulating synchronous buck
DC/DC converters. It was designed especially for DDR DRAM,
SDRAM, graphic chipset applications, and system regulators in
high performance applications.
Voltage-feed-forward ramp modulation, current mode
control, and internal feedback compensation provide fast
response to input voltage and output load transients. Input
current ripple is minimized by channel-to-channel PWM
phase shift of 0°, 90° or 180° (determined by input voltage
and status of the DDR pin).
The ISL6539 can control two independent output voltages
adjustable from 0.9V to 5.5V or, by activating the DDR pin,
transform into a complete DDR memory power supply
solution. In DDR mode, CH2 output voltage VTT tracks CH1
output voltage VDDQ. CH2 output can both source and sink
current, an essential power supply feature for DDR memory.
The reference voltage VREF required by DDR memory is
generated as well.
In dual power supply applications the ISL6539 monitors the
output voltage of both CH1 and CH2. An independent
PGOOD (power good) signal is asserted for each channel
after the soft-start sequence has completed, and the output
voltage is within PGOOD window. In DDR mode CH1
generates the only PGOOD signal.
Built-in overvoltage protection prevents the output from going
above 115% of the set point by holding the lower MOSFET on
and the upper MOSFET off. When the output voltage decays
below the overvoltage threshold, normal operation
automatically resumes. Once the soft-start sequence has
completed, undervoltage protection latches the offending
channel off if the output drops below 75% of its set point value
for the dual switcher. Adjustable overcurrent protection (OCP)
monitors the voltage drop across the r
DS(ON)
of the lower
MOSFET. If more precise current-sensing is required, an
external current sense resistor may be used.
FN9144
Rev 6.00
Apr 29, 2010
Features
• Provides Regulated Output Voltage in the Range of 0.9V
to 5.5V
• Complete DDR Memory Power Solution with VTT Tracks
VDDQ/2 and VDDQ/2 Buffered Reference Output
• Supports both DDR-I and DDR2 Memory
• Lossless r
DS(ON)
Current-Sense Sensing
• Excellent Dynamic Response with Voltage Feed-Forward
and Current Mode Control Accommodating Wide Range
LC Filter Selections
• Dual Mode Operation - Operates Directly from a 5.0V to
15V Input or 3.3V/5V System Rail
• Undervoltage Lock-out on VCC Pin
• Power-good, Overcurrent, Overvoltage, Undervoltage
protection for both Channels
• Synchronized 300kHz PWM Operation in PWM Mode
• Pb-Free (RoHS Compliant)
Applications
• Single and Dual Channel DDR Memory Power Systems
• Graphics Cards - GPU and Memory Supplies
• Supplies for Servers, Motherboards, FPGAs
• ASIC Power Supplies
• Embedded Processor and I/O Supplies
• DSP Supplies
FN9144 Rev 6.00
Apr 29, 2010
Page 1 of 20
ISL6539
Ordering Information
PART
NUMBER
ISL6539IAZ*
(Note)
ISL6539CAZ*
(Note)
PART
MARKING
ISL 6539IAZ
TEMP.
RANGE
(°C)
PACKAGE
PKG.
DWG. #
M28.15
M28.15
Pinout
ISL6539
(28 LD QSOP)
TOP VIEW
GND 1
LGATE1 2
PGND1 3
PHASE1 4
UGATE1 5
BOOT1 6
ISEN1 7
EN1 8
GND 9
VSEN1 10
OCSET1 11
SOFT1 12
DDR 13
VIN 14
28 VCC
27 LGATE2
26 PGND2
25 PHASE2
24 UGATE2
23 BOOT2
22 ISEN2
21 EN2
20 GND
19 VSEN2
18 OCSET2
17 SOFT2
16 PG2/REF
15 PG1
-40 to +85 28 Ld QSOP
(Pb-free)
ISL 6539CAZ -40 to +85 28 Ld QSOP
(Pb-free)
*Add “-T” suffix for tape and reel. Please refer to TB347 for details
on reel specifications.
NOTE: These Intersil Pb-free plastic packaged products employ
special Pb-free material sets, molding compounds/die attach
materials, and 100% matte tin plate plus anneal (e3 termination
finish, which is RoHS compliant and compatible with both SnPb and
Pb-free soldering operations). Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed
the Pb-free requirements of IPC/JEDEC J STD-020.
FN9144 Rev 6.00
Apr 29, 2010
Page 2 of 20
ISL6539
Generic Application Circuits
V
IN
3.3V OR
5.0V TO 15V
OCSET1
Q1
L1
V
OUT1
PWM1
EN1
EN2
5V
VCC
DDR
OCSET2
PWM2
Q4
C2
+
Q3
L2
+
Q2
C1
V
OUT2
FIGURE 1. ISL6539 APPLICATION CIRCUIT FOR TWO CHANNEL POWER SUPPLY
V
IN
3.3V OR
5.0V TO 15V
OCSET1
Q1
L1
VDDQ
+
PWM1
EN1
EN2
5V
VREF
VCC
DDR
PG2/VREF
PWM2
Q2
C1
Q3
L2
VTT
OCSET2
Q4
C2
+
FIGURE 2. ISL6539 APPLICATION CIRCUIT FOR COMPLETE DDR MEMORY POWER SUPPLY
FN9144 Rev 6.00
Apr 29, 2010
Page 3 of 20
ISL6539
Absolute Maximum Ratings
Bias Voltage, VCC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +6.5V
Input Voltage, VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +18.0V
PHASE, UGATE . . . . . . . . . . . . . . . . . .GND - 5V (Note 1) to +24.0V
BOOT, ISEN . . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to +24.0V
BOOT with Respect to PHASE . . . . . . . . . . . . . . . . . . . . . . . . . +6.5V
All Other Pins . . . . . . . . . . . . . . . . . . . . . . GND -0.3V to V
CC
+ 0.3V
Thermal Information
Thermal Resistance (Typical, Note 2)
JA
(°C/W)
QSOP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . .
80
Maximum Junction Temperature (Plastic Package). . . . . . . . +150°C
Maximum Storage Temperature Range . . . . . . . . . .-65°C to +150°C
Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Recommended Operating Conditions
Bias Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5.0V
5%
Input Voltage, VIN . . . . . . . . . . . . . . . . . . . . .+3.3V or 5.0V to +18.0V
Ambient Temperature Range, Commercial . . . . . . . . . 0°C to +70°C
Junction Temperature Range, Commercial . . . . . . . . 0°C to +125°C
Ambient Temperature Range, Industrial . . . . . . . . . .-40°C to +85°C
Junction Temperature Range, Industrial . . . . . . . . .-40°C to +125°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTES:
1. 250ns transient. See “Confining the Negative Phase Node Voltage Swing with Schottky Diode” on page 17.
2.
JA
is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
Electrical Specifications
PARAMETER
VCC SUPPLY
Bias Current
Shut-Down Current
VCC UVLO
Rising VCC Threshold
Falling VCC Threshold
VIN
Input Voltage Pin Current (Sink)
Shut-Down Current
OSCILLATOR
Oscillator Frequency
Recommended Operating Conditions, Unless Otherwise Noted.
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
ICC
ICCSN
LGATEx, UGATEx Open, VSENx forced above
regulation point, DDR = 0, VIN >5V
-
-
1.8
-
3.0
1
mA
µA
VCCU
VCCD
4.30
4.00
4.45
4.14
4.50
4.34
V
V
IVIN
IVINS
-
-
-
-
35
1
µA
µA
fOSC
ISL6539C
ISL6539I
255
245
-
-
-
-
-
300
300
2
0.625
1
125
250
345
345
-
-
-
-
-
kHz
kHz
V
V
V
mV/V
mV/V
Ramp Amplitude, Peak-to-Peak
Ramp Amplitude, Peak-to-Peak
Ramp Offset
Ramp/VIN Gain
Ramp/VIN Gain
REFERENCE AND SOFT-START
Internal Reference Voltage
Reference Voltage Accuracy
Soft-Start Current During Start-Up
Soft-Start Complete Threshold
VR1
VR2
VROFF
GRB1
GRB2
VIN pin voltage = 16V (Note 3)
VIN pin voltage = 5V (Note 3)
(Note 3)
VIN pin voltage > 4.2V (Note 3)
VIN pin voltage
4.1V (Note 3)
VREF
-
-1.0
0.9
-
4.5
1.5
-
+1.0
-
-
V
%
µA
V
ISOFT
VST
(Note 3)
-
-
FN9144 Rev 6.00
Apr 29, 2010
Page 4 of 20
ISL6539
Electrical Specifications
PARAMETER
PWM CONVERTERS
Load Regulation
VSEN Pin Bias Current
Minimum Duty Cycle
Maximum Duty Cycle
Undervoltage Shut-Down Level
Overvoltage Protection
GATE DRIVERS
Upper Drive Pull-Up Resistance
Upper Drive Pull-Down Resistance
Lower Drive Pull-Up Resistance
Lower Drive Pull-Down Resistance
R2UGPUP VCC = 5V
R2UGPDN VCC = 5V
R2LGPUP
R2LGPDN
VCC = 5V
VCC = 5V
-
-
-
-
4
2.3
4
1.1
8
4
8
3
IVSEN
DMIN
DMAX
VUVL
VOVP1
Fraction of the set point; ~2µs noise filter
Fraction of the set point; ~2µs noise filter
0.0mA < IVOUT1 <5.0A; 5.0V < VIN <15.0V
(Note 3)
-2.0
-
-
-
70
110
-
80
4
87
75
115
+2.0
-
-
-
80
-
%
nA
%
%
%
%
Recommended Operating Conditions, Unless Otherwise Noted.
(Continued)
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
POWER GOOD AND CONTROL FUNCTIONS
Power Good Lower Threshold
Power Good Higher Threshold
PGOODx Leakage Current
PGOODx Voltage Low
ISEN Sourcing Current
OCSET Sourcing Current Range
EN - Low (Off)
EN - High (On)
DDR - Low (Off)
DDR - High (On)
DDR REF Output Voltage
DDR REF Output Current
NOTES:
3. Limits should be considered typical and are not production tested.
VDDREF
IDDREF
DDR = 1, IREF = 0...10mA
DDR = 1 (Note 3)
VPG
-
VPG+
IPGLKG
VPGOOD
Fraction of the set point; ~3µs noise filter
Fraction of the set point; ~3µs noise filter.
VPULLUP = 5.5V
IPGOOD = -4mA
(Note 3)
84
110
-
-
-
2
-
2.0
-
3
0.99*
VOC2
-
89
115
-
0.5
-
-
-
-
-
-
VOC2
10
92
120
1
1
260
20
0.8
-
0.8
-
1.01*
VOC2
12
%
%
µA
V
µA
µA
V
V
V
V
V
mA
Functional Pin Description
GND (Pin 1, 9, 20)
Signal ground for the IC. All three ground pins must be
connected to ground for proper IC operation. Connect to the
ground plane through a path as low in inductance as
possible.
be connected to the ground plane through a path as low in
inductance as possible.
PHASE1, PHASE2 (Pin 4, 25)
The PHASE1 and PHASE2 points are the junction points of
the upper MOSFET sources, output filter inductors, and
lower MOSFET drains. Connect these pins to the respective
converter’s upper MOSFET source.
LGATE1, LGATE2 (Pin 2, 27)
Connect these pins to the gates of the corresponding lower
MOSFETs. These pins provide the PWM-controlled gate
drive for the lower MOSFETs.
UGATE1, UGATE2 (Pin 5, 24)
Connect these pins to the gates of the corresponding upper
MOSFETs. These pins provide the PWM-controlled gate
drive for the upper MOSFETs.
PGND1, PGND2 (Pin 3, 26)
These pins provide the return connection for lower gate
drivers, and are connected to sources of the lower
MOSFETs of their respective converters. These pins must
BOOT1, BOOT2 (Pin 6, 23)
These pins power the upper MOSFET drivers of the PWM
converter. Connect these pins to the junction of the bootstrap
FN9144 Rev 6.00
Apr 29, 2010
Page 5 of 20
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