DATASHEET
ISLA118P50
8-Bit, 500MSPS A/D Converter
The ISLA118P50 is a low-power, high-performance, 500MSPS
analog-to-digital converter designed with Intersil’s proprietary
FemtoCharge™
technology on a standard CMOS process. The
ISLA118P50 is part of a pin-compatible portfolio of 8, 10 and
12-bit A/Ds. This device an upgrade of the KAD551XP-50
product family and is pin similar.
The device utilizes two time-interleaved 250MSPS unit A/Ds to
achieve the ultimate sample rate of 500MSPS. A single
500MHz conversion clock is presented to the converter, and all
interleave clocking is managed internally. The proprietary
Intersil Interleave Engine (I2E) performs automatic fine
correction of offset, gain, and sample time skew mismatches
between the unit A/Ds to optimize performance. No external
interleaving algorithm is required.
A serial peripheral interface (SPI) port allows for extensive
configurability of the A/D. The SPI also controls the interleave
correction circuitry, allowing the system to issue continuous
calibration commands as well as configure many dynamic
parameters.
Digital output data is presented in selectable LVDS or CMOS
formats. The ISLA118P50 is available in a 72-contact QFN
package with an exposed paddle. Performance is specified
over the full industrial temperature range (-40°C to +85°C).
FN7565
Rev 2.00
July 25, 2011
Features
• 1.15GHz Analog Input Bandwidth
• 90fs Clock Jitter
• Automatic Fine Interleave Correction Calibration
• Multiple Chip Time Alignment Support via the Synchronous
Clock Divider Reset
• Programmable Gain, Offset and Skew Control
• Over-Range Indicator
• Clock Phase Selection
• Nap and Sleep Modes
• Two’s Complement, Gray Code or Binary Data Format
• DDR LVDS-Compatible or LVCMOS Outputs
• Programmable Test Patterns and Internal Temperature
Sensor
Applications
• Radar and Electronic/Signal Intelligence
• Broadband Communications
• High-Performance Data Acquisition
CLKDIVRSTN
CLKDIVRSTP
Pin-Compatible Family
OVDD
AVDD
MODEL
ISLA112P50
CLKOUTP
CLKOUTN
RESOLUTION
12
10
8
SPEED
(MSPS)
500
500
500
CLKP
CLKN
CLOCK
MANAGEMENT
ISLA110P50
ISLA118P50
SHA
8 -BIT
250MSPS
ADC
VREF
Key Specifications
D[7:0]P
D[7:0]N
• SNR = 49.9dBFS for f
IN
= 190MHz (-1dBFS)
• SFDR = 68dBc for f
IN
= 190MHz (-1dBFS)
• Total Power Consumption = 428mW
ORP
DIGITAL
VINP
VINN
Gain/ Offset/ Skew
Adjustments
ORN
OUTFMT
OUTMODE
I2E
ERROR
CORRECTION
VCM
SHA
8 -BIT
250 MSPS
ADC
VREF
1.25V
+
–
SPI
CONTROL
RESETN
NAPSLP
FIGURE 1. BLOCK DIAGRAM
FN7565 Rev 2.00
July 25, 2011
OGND
AGND
CSB
SCLK
SDIO
SDO
Page 1 of 34
ISLA118P50
Table of Contents
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Thermal Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Recommended Operating Conditions . . . . . . . . . . . . . . . . . . 5
Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Digital Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Switching Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Typical Performance Curves . . . . . . . . . . . . . . . . . . . . . . . . . 10
Theory of Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Power-On Calibration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
User Initiated Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Analog Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Clock Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Jitter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Voltage Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Digital Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Over Range Indicator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Nap/Sleep. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
I2E Requirements and Restrictions . . . . . . . . . . . . . . . . . . .18
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Active Run State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Power Meter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Notch Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Nyquist Zones. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Configurability and Communication . . . . . . . . . . . . . . . . . . . . 19
Clock Divider Synchronous Reset . . . . . . . . . . . . . . . . . . . . 19
Serial Peripheral Interface . . . . . . . . . . . . . . . . . . . . . . . . . . 22
SPI Physical Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SPI Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Device Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Indexed Device Configuration/Control. . . . . . . . . . . . . . . . . .
AC RMS Power Threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Address 0x60-0x64: I2E initialization . . . . . . . . . . . . . . . . . .
Global Device Configuration/Control . . . . . . . . . . . . . . . . . . .
Device Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SPI Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
22
23
23
23
25
25
26
27
28
Equivalent Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
A/D Evaluation Platform . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Layout Considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Split Ground and Power Planes . . . . . . . . . . . . . . . . . . . . . . .
Clock Input Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . .
Exposed Paddle. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Bypass and Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LVDS Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LVCMOS Outputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Unused Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
31
31
31
31
31
31
31
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Package Outline Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
FN7565 Rev 2.00
July 25, 2011
Page 2 of 34
ISLA118P50
Ordering Information
PART NUMBER
(Notes 1, 2)
ISLA118P50IRZ
NOTES:
1. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-
free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
2. For Moisture Sensitivity Level (MSL), please see device information page for
ISLA118P50.
For more information on MSL please see techbrief
TB363.
PART
MARKING
ISLA118P50 IRZ
SPEED
(MSPS)
500
TEMP. RANGE
(°C)
-40 to +85
PACKAGE
(Pb-Free)
72 Ld QFN
PKG.
DWG. #
L72.10x10C
Pin Configuration
ISLA118P50
(72 LD QFN)
TOP VIEW
OUTFMT
AVDD
OVSS
AVSS
OVDD
56
SCLK
SDIO
SDO
ORP
ORN
D7N
D6N
D7P
72
AVDD
DNC
RES
RES
DNC
AVDD
AVSS
AVSS
VINN
1
2
3
4
5
6
7
8
9
71
70
69
68
67
66
65
64
63
62
61
D6P
60
59
58
D5N
57
55
54
D4P
53
D4N
52
D3P
51
D3N
50
D2P
49
D2N
48
CLKOUTP
47
CLKOUTN
46
RLVDS
PD
VINP 10
AVSS 11
AVDD 12
DNC 13
DNC 14
VCM 15
DNC 16
DNC 17
DNC 18
19
20
21
22
23
24
25
26
27
r
OVSS
45
OVSS
44
D1P
43
D1N
42
D0P
41
D0N
40
DNC
39
DNC
38
DNC
37
DNC
36
CSB
ion
at
rm
nfo
I
al
nti
ide
nf
CONNECT THERMAL PAD TO AVSS
28
29
30
31
32
33
34
35
CLKDIVRSTP
CLKDIVRSTN
OUTMODE
NAPSLP
RESETN
OVDD
DNC
DNC
DNC
DNC
D5P
DNC
CLKP
DNC
FIGURE 2. PIN CONFIGURATION
FN7565 Rev 2.00
July 25, 2011
OVDD
AVDD
AVDD
OVSS
CLKN
Page 3 of 34
ISLA118P50
Pin Descriptions
PIN NUMBER
1, 6, 12, 19, 24, 71
2, 5, 13, 14, 16, 17, 18, 30,
31, 32, 33, 34, 35, 37, 38, 39,
40
3, 4
7, 8, 11, 72
9, 10
15
20, 21
22
23
25
26, 45, 55, 65
27, 36, 56
28, 29
41, 42
43, 44
46
47, 48
49, 50
51, 52
53, 54
57, 58
59, 60
61, 62
63, 64
66
67
68
69
70
PD
LVDS [LVCMOS] NAME
AVDD
DNC
1.8V Analog Supply
Do Not Connect
LVDS [LVCMOS] FUNCTION
RES
AVSS
VINN, VINP
VCM
CLKP, CLKN
OUTMODE
NAPSLP
RESETN
OVSS
OVDD
CLKDIVRSTP,
CLKDIVRSTN
D0N, D0P [NC, D0]
D1N, D1P [NC, D1]
RLVDS
CLKOUTN, CLKOUTP [NC,
CLKOUT]
D2N, D2P [NC, D2]
D3N, D3P [NC, D3]
D4N, D4P [NC, D4]
D5N, D5P [NC, D5]
D6N, D6P [NC, D6]
D7N, D7P [NC, D7]
ORN, ORP [NC, OR]
SDO
CSB
SCLK
SDIO
OUTFMT
AVSS
Reserved. (4.7k pull-up to OVDD is required for each of these pins)
Analog Ground
Analog Input Negative, Positive
Common Mode Output
Clock Input True, Complement
Tri-Level Output Mode (LVDS, LVCMOS)
Tri-Level Power Control (Nap, Sleep modes)
Power On Reset (Active Low)
Output Ground
1.8V Output Supply
Sample Clock Synchronous Divider Reset Positive, Negative
LVDS Bit 0 Output Complement, True [NC, LVCMOS Bit 0]
LVDS Bit 1 Output Complement, True [NC, LVCMOS Bit 1]
LVDS Bias Resistor (connect to OVSS with a 10k, 1% resistor)
LVDS Clock Output Complement, True [NC, LVCMOS CLKOUT]
LVDS Bit 2 Output Complement, True [NC, LVCMOS Bit 2]
LVDS Bit 3 Output Complement, True [NC, LVCMOS Bit 3]
LVDS Bit 4 Output Complement, True [NC, LVCMOS Bit 4]
LVDS Bit 5 Output Complement, True [NC, LVCMOS Bit 5]
LVDS Bit 6 Output Complement, True [NC, LVCMOS Bit 6]
LVDS Bit 7 (MSB) Output Complement, True [NC, LVCMOS Bit 7]
LVDS Over Range Complement, True [NC, LVCMOS Over Range]
SPI Serial Data Output (4.7k pull-up to OVDD is required)
SPI Chip Select (active low)
SPI Clock
SPI Serial Data Input/Output
Tri-Level Output Data Format (Two’s Comp., Gray Code, Offset Binary)
Exposed Paddle - Analog Ground
NOTE: LVCMOS Output Mode Functionality is shown in brackets (NC = No Connection)
FN7565 Rev 2.00
July 25, 2011
Page 4 of 34
ISLA118P50
Absolute Maximum Ratings
AVDD to AVSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.4V to 2.1V
OVDD to OVSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.4V to 2.1V
AVSS to OVSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 0.3V
Analog Inputs to AVSS . . . . . . . . . . . . . . . . . . . . . . . . . -0.4V to AVDD + 0.3V
Clock Inputs to AVSS . . . . . . . . . . . . . . . . . . . . . . . . . . -0.4V to AVDD + 0.3V
Logic Input to AVSS . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.4V to OVDD + 0.3V
Logic Inputs to OVSS . . . . . . . . . . . . . . . . . . . . . . . . . . -0.4V to OVDD + 0.3V
Thermal Information
Thermal Resistance (Typical)
JA
(°C/W)
JC
(°C/W)
72 Ld QFN (Notes 3, 4, 5) . . . . . . . . . . . . . .
23
0.75
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+150°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Recommended Operating Conditions
Operating Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
3.
JA
is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech
Brief
TB379
for details.
4. For
JC
, the “case temp” location is the center of the exposed metal pad on the package underside.
5. For solder stencil layout and reflow guidelines, please see Tech Brief
TB389.
Electrical Specifications
All specifications apply under the following conditions unless otherwise noted: AVDD = 1.8V, OVDD = 1.8V,
T
A
= -40°C to +85°C (typical specifications at +25°C), A
IN
= -1dBFS, F
IN
= 105MHz, f
SAMPLE
= 500MSPS, after completion of I2E calibration.
ISLA118P50
(Note 6)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DC SPECIFICATIONS (Note 6)
Analog Input
Full-Scale Analog Input Range
Input Resistance
Input Capacitance
Full Scale Range Temp. Drift
Input Offset Voltage
Gain Error
Common-Mode Output Voltage
V
FS
R
IN
C
IN
A
VTC
V
OS
E
G
V
CM
435
Differential
Differential
Differential
Full Temp
-10
1.41
1.45
500
1.9
325
±2.0
±2.0
535
635
10
1.52
V
P-P
pF
ppm/°C
mV
%
mV
Clock Inputs
Inputs Common Mode Voltage
CLKP, CLKN Input Swing
0.2
0.9
1.8
V
V
Power Requirements
1.8V Analog Supply Voltage
1.8V Digital Supply Voltage
1.8V Analog Supply Current
1.8V Digital Supply Current (Note 7)
AVDD
OVDD
IAVDD
I
OVDD
3mA LVDS, I2E powered down, Notch
Filter powered down
3mA LVDS, I2E On, Notch Filter On
Power Supply Rejection Ratio
PSRR
30MHz, 200mV
P-P
1.7
1.7
1.8
1.8
173
72
117
-36
1.9
1.9
186
79
V
V
mA
mA
mA
dB
Total Power Dissipation
FN7565 Rev 2.00
July 25, 2011
Page 5 of 34
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