AS7620 Evaluation Board
1 General Description
A demonstration board is available to test AS7620
functionalities and performance in a standard
application.
Default conditions are V
IN
=24V and V
OUT
=5V, but in
principle the input voltage can range from 5V to 32V.
While the AS7620 output voltage can range from 1.2V to
V
IN
, the demonstration board upper output voltage
limitation is 15V.
The output voltage can be easily adjusted using the
0805-sized output resistor divider pads on the back of
the evaluation board.
DemoBoard Data Sheet
5 0 0 m A H y s t e r e t i c H i g h Vo l ta g e St e p - D o w n C o n v e r t e r
with Dual Power Monitor
2 Key Features
Convenient test point loops for input, output,
shutdown and power monitor flags
High Voltage ceramic capacitor for output voltages
of up to 15V
Micro-power LDO generates 3.3V for flag outputs,
supplies up to 250mA
Single-sided assembly allows convenient backside
access for modification
Large-size 0805 parallel pads for all configuration
resistors
Alternate landing pads for output inductor and
capacitor
Quiet GND probe point minimizes GND loop area
and noise
Figure 1. Demo Board Photograph
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Revision 1.00
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AS7620 Evaluation Board
DemoBoard Data Sheet - S c h e m a t i c & B O M
3 Schematic & BOM
In
Figure 2,
the bold lines indicate high current paths. Components placed on both TOP and BOTTOM side are
highlighted in the schematic.
Figure 2. Schematic and BOM
(3.3V)
Vbias
Vbias
tp-rct
TP1
tp-rct
TP2
tp-rct
TP3
tp-rct
PF
9
R5
2.7M
R60
2M
R6
100K
R40
R30
(24V)
VIN
VIN
tp-rct
C1
4.7µF
GND
tp-rct
C3
0.1µF
R7
R4
150K
R3
2.2M
8
7
10
11
12
Pad
1
6
5
4
C6
1µF
U2A
2
SHDN
TP4
PG
tp-rct
NoPoP
R9
0Ω
(5.0V)
VOUT
3
VOUT
C5
0.1µF
tp-rct
+
-
1
AS1360-33-T
AS7620-A
NoPoP
R8
0Ω
R1
931K
C4
47pF
R2
287K
R20
C20
C2
100µF
GND1
tp-rct
R10
C40
U1
2
3
L10
L1 10µH
D
1
MA22D39
Note:
High current path indicated with bold blue line
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Revision 1.00
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AS7620 Evaluation Board
DemoBoard Data Sheet - L a y o u t & C o m p o n e n t P l a c e m e n t
4 Layout & Component Placement
The layout must be drawn properly in order to minimize the noise, which can affect the behaviour of the converter itself
and/or other electronic stages located nearby. The following high current path can be identified:
1. Input Power
2. Output Power
3. GND
4. Switching node (LX)
In order to maximize the efficiency and minimize the noise generated by pulsed currents, the above traces must be as
wide and short as possible. Special attention must be paid when positioning the FB trace, which will carry the output
voltage information into the device. The FB trace must be away from the switching node and, possibly, shielded by a
GND trace in between.
Figure 3. Layout TOP Side
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AS7620 Evaluation Board
DemoBoard Data Sheet - L a y o u t & C o m p o n e n t P l a c e m e n t
Figure 4. Layout BOTTOM Side
All components that are changing the operating characteristics of the AS7620 have optional parallel access pads on
the back-side. Larger size 0805 surface mount resistors and capacitors can be soldered in parallel to the default
components. Output capacitor and inductor also have mirrored pads to more conveniently change the component
value. With the default resistor still in place, the effective resistor value is calculated as follows:
1
1 1
R
∗
R
-
-
(1/R_eff =
-- + -----
) or R_eff =
---------------
1
R R
1
R
+
R
(EQ 1)
The schematic identifies optional parallel components with a ‘zero’ added to the component index, for example R10 is
in parallel to R1. Additionally, the access pads may be used to probe certain nodes in the circuit that are not already
connected to a test point.
Figure 5. Placement TOP
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AS7620 Evaluation Board
DemoBoard Data Sheet - L a y o u t & C o m p o n e n t P l a c e m e n t
Testing switch-mode converters requires attention to probe placement, in particular GND connections. It is best
practice to use the most sensitive GND connection as a single point GND reference. Pin 4 of the AS7620 is the
recommended GND connection and TP4 has been located very close to it to minimize GND loop currents. Because of
high-frequency content of the switching frequencies, it is best to use a short GND strap connected closely to the probe
pin and connect it to TP4, which is labelled with a GND symbol on the front.
Figure 6. Placement BOTTOM
Bias Voltage
A stable 3.3V derived from V
OUT
by the ‘austriamicrosystems’ ultra-low power linear regulator (AS1360) is available on
board to pull up the PGOOD, PF and ILIM pin. In general those pins can accept a pull up voltage up to 3.6V. Vbias is
accessible by the related terminal on the board. The AS1360 delivers up to 250mA and therefore can also be used to
post-regulate the output voltage of the AS7620, effectively removing ripple voltage and hysteretic switching artefacts.
Please consult the AS1360 datasheet for optimizing the output voltage of the AS7620 to accommodate the drop-out
voltage of the AS1360 for most efficient power conversion performance.
Power Good
The PG output comes outside with a dedicated terminal on the board. If the output voltage is not lower than 93% (typ)
of the set point, the internal open drain will be off.
Early Power Fail
The input voltage is monitored by the V
EPF
pin and a dedicated flag (PF active low) is provided outside. The status of
PF depends on the programmed threshold and hysteresis.
Table 1
provides the resistors values covering all the
standard input BUS. The resistors values are 1% commercial values. It is mandatory to use the correct resistors values
to guarantee the respect of maximum absolute voltages at EPF and PF pin. V
DD
has been considered 3.3V.
Terminology:
VRST: Reset voltage for the EPF. It is 90% of the Input BUS voltage.
VTRIP: Trip voltage for the EPF. It is 80% of the Input BUS voltage.
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