Si4320 Universal ISM
Band FSK Receiver
DESCRIPTION
Silicon Labs’ Si4320 is a single chip, low power, multi-channel FSK
receiver designed for use in applications requiring FCC or ETSI
conformance for unlicensed use in the 315, 433, 868, and 915 MHz
bands. Used in conjunction with Si4220/21, Silicon Labs’ FSK
transmitters, the Si4320 is a flexible, low cost, and highly integrated
solution that does not require production alignments. All required RF
functions are integrated. Only an external crystal and bypass filtering are
needed for operation.
The Si4320 has a completely integrated PLL for easy RF design, and its
rapid settling time allows for fast frequency hopping, bypassing multipath
fading, and interference to achieve robust wireless links. The PLL’s high
resolution allows the usage of multiple channels in any of the bands. The
baseband bandwidth (BW) is programmable to accommodate various
deviation, data rate, and crystal tolerance requirements. The receiver
employs the Zero-IF approach with I/Q demodulation, therefore no external
components (except crystal and decoupling) are needed in a typical
application. The Si4320 is a complete analog RF and baseband receiver
including a multi-band PLL synthesizer with an LNA, I/Q down converter
mixers, baseband filters and amplifiers, and I/Q demodulator.
The chip dramatically reduces the load on the microcontroller with
integrated digital data processing: data filtering, clock recovery, data
pattern recognition and integrated FIFO. The automatic frequency control
(AFC) feature allows using a low accuracy (low cost) crystal. To minimize
the system cost, the chip can provide a clock signal for the microcontroller,
avoiding the need for two crystals.
For simple applications, the receiver supports a standalone operation
mode. This allows complete data receiver operation and control of four
digital outputs based on the incoming data pattern without a
microcontroller. In this mode, 12 or more predefined frequency channels
can be used in any of the four bands. For low power applications, the
device supports low duty-cycle operation based on the internal wake-up
timer.
Si4320
PIN ASSIGNMENT
Standalone Mode
Microcontroller Mode
This document refers to Si4320-IC Rev
J1.
See www.silabs.com/integration for any applicable
errata. See back page for ordering information.
FEATURES
Fully integrated (low BOM, easy design-in)
No alignment required in production
Fast settling, programmable, high-resolution PLL
Fast frequency hopping capability
High bit rate (up to 115.2 kbps in digital mode and 256 kbps
in analog mode)
Direct differential antenna input
Programmable baseband bandwidth (67 to 400 kHz)
Analog and digital RSSI outputs
Automatic frequency control (AFC)
Data quality detection (DQD)
Internal data filtering and clock recovery
RX pattern recognition
SPI compatible serial control interface
Clock and reset signals for microcontroller
16 bit RX data FIFO
Standalone operation mode without microcontroller
Low power duty-cycle mode (less than 0.5 mA average
supply current)
Standard 10 MHz crystal reference with in circuit calibration
Alternative OOK support
Wake-up timer
Low battery detector
2.2 to 5.4 V supply voltage
Low power consumption (~9 mA in low bands)
Low standby current (0.3 µA)
Compact 16-pin TSSOP package
FUNCTIONAL BLOCK DIAGRAM
TYPICAL APPLICATIONS
Remote control
Home security and alarm
Wireless keyboard/mouse and other PC peripherals
Toy control
Remote keyless entry
Tire pressure monitoring
Telemetry
Personal/patient data logging
Remote automatic meter reading
1
Si4320-DS Rev 1.5r 0308
www.silabs.com
Si4320
DETAILED DESCRIPTION
General
The Si4320 FSK receiver is the counterpart of the Si4220 FSK
transmitter. It covers the unlicensed frequency bands at 315,
433, 868, and 915 MHz. The device facilitates compliance with
FCC and ETSI requirements.
The receiver employs the Zero-IF approach with I/Q
demodulation, allowing the use of a minimal number of external
components in a typical application. The Si4320 consists of a
fully integrated multi-band PLL synthesizer, an LNA with
switchable gain, I/Q down converter mixers, baseband filters and
amplifiers, and an I/Q demodulator followed by a data filter.
Data Filtering and Clock Recovery
The output data filtering can be completed by an external
capacitor or by using digital filtering according to the final
application.
Analog operation:
The filter is an RC type low-pass filter and a
Schmitt-trigger (St). The resistor (10k) and the St is integrated on
the chip. An (external) capacitor can be chosen according to the
actual bit-rate. In this mode the receiver can handle up to 256
kbps data rate.
Digital operation:
The data filter is a digital realization of an
analog RC filter followed by a comparator with hysteresis. In this
mode there is a clock recovery circuit (CR), which can provide
synchronized clock to the data. With this clock the received data
can fill the RX Data FIFO. The CR has three operation modes:
fast, slow, and automatic. In slow mode, its noise immunity is
very high, but it has slower settling time and requires more
accurate data timing than in fast mode. In automatic mode the
CR automatically changes between fast and slow modes. The CR
starts in fast mode, then automatically switches to slow mode
after locking.
(Only the data filter and the clock recovery use the bit-rate clock.
Therefore, in analog mode, there is no need for setting the
correct bit-rate.)
PLL
The programmable PLL synthesizer determines the operating
frequency, while preserving accuracy based on the on-chip
crystal-controlled reference oscillator. The PLL’s high resolution
allows for the use of multiple channels in any of the bands.
The RF VCO in the PLL performs automatic calibration, which
requires only a few microseconds. Calibration always occurs
when the synthesizer begins. If temperature or supply voltage
changes significantly or operational band has changed, VCO
recalibration is recommended. Recalibration can be initiated at
any time by switching the synthesizer off and back on again.
Data Validity Blocks
RSSI
A digital RSSI output is provided to monitor the input signal level.
It goes high if the received signal strength exceeds a given
preprogrammed level. An analog RSSI signal is also available.
The RSSI settling time depends on the filter capacitor used.
Voltage on ARRSI pin vs. Input RF power
LNA
The LNA has 250 Ohm input impedance, which works well with
the recommended antennas. (See Application Notes available
from www.silabs.com/integration.)
If the RF input of the chip is connected to 50 Ohm devices, an
external matching circuit is required to provide the correct
matching and to minimize the noise figure of the receiver.
The LNA gain (and linearity) can be selected (0, –6, –14, –20 dB
relative to the highest gain) according to RF signal strength. This
is useful in an environment with strong interferers.
Baseband Filters
The receiver bandwidth is selectable by programming the
bandwidth (BW) of the baseband filters. This allows setting up
the receiver according to the characteristics of the signal to be
received.
An appropriate bandwidth can be selected to accommodate
various FSK deviation, data rate, and crystal tolerance
requirements. The filter structure is a 7-th order Butterworth low-
pass with 40 dB suppression at 2*BW frequency. Offset
cancellation is accomplished by using a high-pass filter with a
cut-off frequency below 7 kHz. See Measurement Results section
for measured receiver selectivity curves.
P1
P2
P3
P4
-65 dBm
-65 dBm
-100 dBm
-100 dBm
1300 mV
1000 mV
600 mV
300 mV
2
Si4320
DQD
The Data Quality Detector monitors the I/Q output of the
baseband amplifier chain by counting the consecutive correct 0-
>1, 1->0 transitions. The DQD output indicates the quality of the
signal to be demodulated. Using this method it is possible to
"forecast" the probability of BER degradation. The programmable
DQD parameter defines the threshold for signaling the good/bad
data quality by the digital one-bit DQD output. In cases when the
deviation is close to the bitrate, there should be four transitions
during a single one bit period in the I/Q signals. As the bitrate
decreases in comparison to the deviation, more and more
transitions will happen during a bitperiod.
Event Handling
In order to minimize current consumption, the receiver supports
the sleep mode. Active mode can be initiated by several wake-up
events (wake-up timer timeout, low supply voltage detection, on-
chip FIFO filled up or receiving a request through the serial
interface).
If any wake-up event occurs, the wake-up logic generates an
interrupt signal, which can be used to wake up the
microcontroller,
effectively
reducing
the
period
the
microcontroller has to be active. The cause of the interrupt can
be read out from the receiver by the microcontroller through the
SDO pin.
AFC
By using an integrated Automatic Frequency Control (AFC)
feature, the receiver can synchronize its local oscillator to the
received signal, allowing the use of:
inexpensive, low accuracy crystals
narrower receiver bandwidth (i.e. increased sensitivity)
higher data rate
Interface and Controller
An SPI compatible serial interface lets the user select the
frequency band, center frequency of the synthesizer, and the
bandwidth of the baseband signal path. Division ratio for the
microcontroller clock, wake-up timer period, and low supply
voltage detector threshold are also programmable. Any of these
auxiliary functions can be disabled when not needed. All
parameters are set to default after power-on; the programmed
values are retained during sleep mode. The interface supports
the read-out of a status register, providing detailed information
about the status of the receiver and the received data. It is also
possible to store the received data bits into the 16bit RX FIFO
register and read them out in a buffered mode. FIFO mode can
be enabled through the SPI compatible interface by setting the
fe
bit to 1 in the Output and FIFO Mode Command.
Crystal Oscillator
The chip has a single-pin crystal oscillator circuit, which provides
a 10 MHz reference signal for the PLL. To reduce external parts
and simplify design, the crystal load capacitor is internal and
programmable. Guidelines for selecting the appropriate crystal
can be found later in this datasheet. The receiver can supply the
clock signal for the microcontroller, so accurate timing is possible
without the need for a second crystal.
When the microcontroller turns the crystal oscillator off by
clearing the appropriate bit using the Configuration Setting
Command, the chip provides a fixed number (128) of further
clock pulses (“clock tail”) for the microcontroller to let it go to idle
or sleep mode.
Standalone Operation Mode
The chip also provides a standalone mode, which allows the use
of the receiver without a microcontroller. This mode can be
selected by connecting the CLK/LPDM pin to either VDD or VSS.
After power on, the chip will check this pin. If it is connected to
any supply voltage, then the chip will go to standalone mode.
Otherwise, it will go to microcontroller mode and the pin will
become an output and provide a clock signal for the
microcontroller. To prevent the Si4320 from accidentally entering
a standalone mode, the stray capacitance should be kept below
50 pF on pin 8.
In this mode operating parameters can be selected from a
limited set by “programming” the receiver over its pins. The chip
is addressable and four digital output pins can be controlled by
the received data. Selecting the Low Power Duty-Cycle Mode
(LPDM) the chip consumes less than 0.5 mA average current.
Low Battery Voltage Detector
The low battery detector circuit monitors the supply voltage and
generates an interrupt if it falls below a programmable threshold
level. The detector circuit has 50 mV hysteresis.
Wake-Up Timer
The wake-up timer has very low current consumption (1.5 µA
typical) and can be programmed from 1 ms to several days with
an accuracy of ±10%.
It calibrates itself to the crystal oscillator at every startup. When
the crystal oscillator is switched off, the calibration circuit
switches it back on only long enough for a quick calibration (a
few milliseconds) to facilitate accurate wake-up timing.
3
Si4320
PACKAGE PIN DEFINITIONS, MICROCONTROLLER MODE
Pin type key: D=digital, A=analog, S=supply, I=input, O=output, IO=input/output
Microcontroller Mode Pin Assignment
Pin
1
2
3
4
5
6
Name
SDI
SCK
nSEL
FFIT/SDO
nIRQ
DATA
nFFS
DCLK
Type
DI
DI
DI
DO
DO
DO
DI
DO
AIO
DO
DO
AIO
DO
S
AI
AI
S
AO
DO
Function
Data input of serial control interface
Clock input of serial control interface
Chip select input of three-wire control interface (active low)
FIFO IT (active low) or serial data out for Status Read Command.
Tristate with bushold cell if nSEL=H
Interrupt request output, (active low)
Received data output (FIFO not used)
FIFO select input (active low)
Received data clock output
(Digital filter used, FIFO not used)
External data filter capacitor connection (Analog filter used)
FIFO IT (active high)
FIFO empty function can be achieved when FIFO IT level is set to one
Clock output for the microcontroller
Crystal connection (other terminal of crystal to VSS) / External reference
input
Reset output (active low)
Negative supply voltage
RF differential signal input
RF differential signal input
Positive supply voltage
Analog RSSI output
Valid Data Indicator output
7
CFIL
FFIT
8
9
10
11
12
13
14
15
16
CLK
XTL/REF
nRES
VSS
IN2
IN1
VDD
ARSSI
VDI
4
Si4320
Typical Application, Microcontroller Mode
Minimal Microcontroller Mode
VCC
C2
10n
C1
2.2u
P4
P3
P2
P1
P0
nRESET CLKin
2
nSEL 3
SDO 4
nIRQ 5
nFFS 6
FFIT 7
8
(optional)
(optional)
SDI
SCK
1
IA4320
16 VDI
15 ARSSI
14
13
12
11
10
9
C3
Antenna
250 Ohm
X1
10MHz
Microcontroller Mode with FIFO usage
VCC
C2
10n
C1
2.2u
P4
P3
P2
P1
P0
1
SDI
SCK 2
nSEL 3
SDO 4
nIRQ
nFFS
FFIT
5
6
7
8
IA4320
nRESET CLKin
16 VDI
15 ARSSI
14
13
12
11
10
9
C3
Antenna
250 Ohm
(optional)
(optional)
X1
10MHz
Note:
For detailed information about the supply decoupling capacitors see page 7.
5
FPGA/CPLD
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