Data Sheet
FEATURES
Stereo, 24-bit analog-to-digital and digital-to-analog converters
DAC SNR: 100 dB (A-weighted), THD: −80 dB at 48 kHz, 3.3 V
ADC SNR: 90 dB (A-weighted), THD: −80 dB at 48 kHz, 3.3 V
Stereo line inputs
Low power
7 mW stereo playback (1.8 V/1.5 V supplies)
14 mW record and playback (1.8 V/1.5 V supplies)
Low supply voltages
Analog: 1.8 V to 3.6 V
Digital: 1.5 V to 3.6 V
256/384 oversampling rate in normal mode;
250/272 oversampling rate in USB mode
Audio sampling rates: 8 kHz, 11.025 kHz, 12 kHz, 16 kHz,
22.05 kHz, 24 kHz, 32 kHz, 44.1 kHz, 48 kHz, 88.2 kHz,
and 96 kHz
20-lead, 4 mm × 4 mm LFCSP (QFN) package
Low Power Audio Codec
SSM2604
GENERAL DESCRIPTION
The SSM2604 is a low power, high quality stereo audio codec
for portable digital audio applications with one set of stereo
programmable gain amplifier (PGA) line inputs. It features two
24-bit analog-to-digital converter (ADC) channels and two
24-bit digital-to-analog (DAC) converter channels.
The SSM2604 can operate as a master or a slave. It supports
various master clock frequencies, including 12 MHz or 24 MHz
for USB devices; standard 256 f
S
or 384 f
S
based rates, such as
12.288 MHz and 24.576 MHz; and many common audio sam-
pling rates, such as 96 kHz, 88.2 kHz, 48 kHz, 44.1 kHz, 32 kHz,
24 kHz, 22.05 kHz, 16 kHz, 12 kHz, 11.025 kHz, and 8 kHz.
The SSM2604 can operate at power supplies as low as 1.8 V for
the analog circuitry and as low as 1.5 V for the digital circuitry.
The maximum voltage supply is 3.6 V for all supplies.
The SSM2604 is specified over the industrial temperature range
of −40°C to +85°C. It is available in a 20-lead, 4 mm × 4 mm
lead frame chip scale package (LFCSP).
APPLICATIONS
Mobile phones
MP3 players
Portable gaming
Portable electronics
Educational toys
AVDD
VMID
AGND
DVDD DGND
FUNCTIONAL BLOCK DIAGRAM
SSM2604
BYPASS
–34.5dB TO +33dB,
1.5dB STEP
RLINEIN
ADC
DAC
ROUT
DIGITAL
PROCESSOR
LLINEIN
–34.5dB TO +33dB,
1.5dB STEP
ADC
DAC
LOUT
BYPASS
CLK
DIGITAL AUDIO INTERFACE
CONTROL INTERFACE
MCLK/ XTO CLKOUT
XTI
PBDAT RECDAT BCLK PBLRC RECLRC SDIN
SCLK
Figure 1.
Rev. A
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Trademarks and registered trademarks are the property of their respective owners.
06978-001
SSM2604
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Digital Filter Characteristics ....................................................... 4
Timing Characteristics ................................................................ 5
Absolute Maximum Ratings ............................................................ 7
Thermal Resistance ...................................................................... 7
ESD Caution .................................................................................. 7
Pin Configuration and Function Descriptions ............................. 8
Typical Performance Characteristics ............................................. 9
Converter Filter Response ........................................................... 9
Digital De-Emphasis .................................................................. 10
Theory of Operation ...................................................................... 11
Digital Core ................................................................................. 11
ADC and DAC ............................................................................ 11
ADC High-Pass and DAC De-Emphasis Filters .................... 11
Data Sheet
Analog Interface ......................................................................... 12
Digital Audio Interface .............................................................. 12
Software Control Interface ........................................................ 15
Control Register Sequencing .................................................... 15
Typical Application Circuits ......................................................... 16
Register Map ................................................................................... 17
Register Map Details ...................................................................... 18
Left-Channel ADC Input Volume, Address 0x00 .................. 18
Right-Channel ADC Input Volume, Address 0x01 ............... 19
Analog Audio Path, Address 0x04 ........................................... 20
Digital Audio Path, Address 0x05 ............................................ 20
Power Management, Address 0x06 .......................................... 21
Digital Audio I/F, Address 0x07 ............................................... 22
Sampling Rate, Address 0x08.................................................... 22
Active, Address 0x09 .................................................................. 25
Software Reset, Address 0x0F ................................................... 25
Outline Dimensions ....................................................................... 26
Ordering Guide .......................................................................... 26
REVISION HISTORY
6/13—Rev. 0 to Rev. A
Changes to Table 8 ............................................................................. 7
Added Control Register Sequencing Section ...............................15
Updated Outline Dimensions ........................................................26
7/08—Revision 0: Initial Version
Rev. A | Page 2 of 28
Data Sheet
SPECIFICATIONS
T
A
= 25°C, AVDD = DVDD = 3.3 V, 1 kHz signal, f
S
= 48 kHz, PGA gain = 0 dB, 24-bit audio data, unless otherwise noted.
Table 1.
Parameter
RECOMMENDED OPERATING CONDITIONS
Analog Voltage Supply (AVDD)
Digital Power Supply
Ground (AGND, DGND)
POWER CONSUMPTION
Power-Up
Stereo Record (1.5 V and 1.8 V)
Stereo Record (3.3 V)
Stereo Playback (1.5 V and 1.8 V)
Stereo Playback (3.3 V)
Power-Down
LINE INPUT
Input Signal Level (0 dB)
Input Impedance
Min
1.8
1.5
Typ
3.3
3.3
0
Max
3.6
3.6
Unit
V
V
V
Conditions
SSM2604
7
22
7
22
56
1 × AVDD/3.3
200
10
480
10
90
84
−80
−75
80
0
1.5
−80
mW
mW
mW
mW
μW
V rms
kΩ
kΩ
kΩ
pF
dB
dB
dB
dB
dB
dB
dB
dB
PGA gain = 0 dB
PGA gain = +33 dB
PGA gain = −34.5 dB
PGA gain = 0 dB, AVDD = 3.3 V
PGA gain = 0 dB, AVDD = 1.8 V
−1 dBFS input, AVDD = 3.3 V
−1 dBFS input, AVDD = 1.8 V
Input Capacitance
Signal-to-Noise Ratio (A-Weighted)
Total Harmonic Distortion (THD)
Channel Separation
Programmable Gain
Gain Step
Mute Attenuation
LINE OUTPUT
DAC
Full-Scale Output
Signal-to-Noise Ratio (A-Weighted)
THD + N
Power Supply Rejection Ratio
Channel Separation
LINE INPUT TO LINE OUTPUT
Full-Scale Output Voltage
Signal-to-Noise Ratio (A-Weighted)
Total Harmonic Distortion
Power Supply Rejection
70
−34.5
+33.5
−1 dBFS input DAC + line output
85
1 × AVDD/3.3
100
94
−80
−75
50
80
1 × AVDD/3.3
92
86
−80
−80
50
V rms
dB
dB
dB
dB
dB
dB
V rms
dB
dB
dB
dB
dB
AVDD = 3.3 V
AVDD = 1.8 V
AVDD = 3.3 V
AVDD = 1.8 V
−75
AVDD = 3.3 V
AVDD = 1.8 V
AVDD = 3.3 V
AVDD = 1.8 V
Rev. A | Page 3 of 28
SSM2604
DIGITAL FILTER CHARACTERISTICS
Table 2.
Parameter
ADC FILTER
Pass Band
Pass-Band Ripple
Stop Band
Stop-Band Attenuation
High-Pass Filter Corner Frequency
Min
0
0.5 f
S
±0.04
0.555 f
S
−61
3.7
10.4
21.6
0
0.5 f
S
Pass-Band Ripple
Stop Band
Stop-Band Attenuation
CORE CLOCK TOLERANCE
Frequency Range
Jitter Tolerance
±0.04
0.555 f
S
−61
8.0
50
13.8
0.445 f
S
Typ
Max
0.445 f
S
Unit
Hz
Hz
dB
Hz
dB
Hz
Hz
Hz
Hz
Hz
dB
Hz
dB
MHz
ps
Conditions
±0.04 dB
−6 dB
Data Sheet
f > 0.567 f
S
−3 dB
−0.5 dB
−0.1 dB
±0.04 dB
−6 dB
DAC FILTER
Pass Band
f > 0.565 f
S
Rev. A | Page 4 of 28
Data Sheet
TIMING CHARACTERISTICS
Table 3. I
2
C Timing
Parameter
t
SCS
t
SCH
t
PH
t
PL
f
SCLK
t
DS
t
DH
t
RT
t
FT
t
HCS
t
MIN
600
600
600
1.3
0
100
Limit
t
MAX
Unit
ns
ns
ns
μs
kHz
ns
ns
ns
ns
ns
t
SCH
t
PL
SCLK
SSM2604
526
900
300
300
600
Description
Start condition setup time
Start condition hold time
SCLK pulse width high
SCLK pulse width low
SCLK frequency
Data setup time
Data hold time
SDIN and SCLK rise time
SDIN and SCLK fall time
Stop condition setup time
SDIN
t
HCS
t
DS
t
PH
t
DH
t
FT
t
SCS
06978-036
06978-025
t
RT
Figure 2. I
2
C Timing
Table 4. Digital Audio Interface Slave Mode Timing
Parameter
t
DS
t
DH
t
LRSU
t
LRH
t
DD
t
BCH
t
BCL
t
BCY
t
MIN
10
10
10
10
25
25
50
Limit
t
MAX
Unit
ns
ns
ns
ns
ns
ns
ns
ns
t
BCH
BCLK
PBLRC/
RECLRC
30
Description
PBDAT setup time from BCLK rising edge
PBDAT hold time from BCLK rising edge
RECLRC/PBLRC setup time to BCLK rising edge
RECLRC/PBLRC hold time to BCLK rising edge
RECDAT propagation delay from BCLK falling edge (external load of 70 pF)
BCLK pulse width high
BCLK pulse width low
BCLK cycle time
t
BCL
t
BCY
t
DS
t
LRH
PBDAT
t
LRSU
t
DH
t
DD
RECDAT
Figure 3. Digital Audio Interface Slave Mode Timing
Rev. A | Page 5 of 28
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