time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are
advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the
product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not
authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
Integrated Silicon Solution, Inc. – www.issi.com
Rev. B, 07/04/2013
3
IS31SE5001
ABSOLUTE MAXIMUM RATINGS
Supply voltage, V
CC
Voltage at any input pin
Operating temperature range, T
A
Storage temperature range, T
STG
-0.3V
~ +6.0V
-0.3V
~ V
CC
+0.3V
-40°C
~ +85°C
-40°C
~ +85°C
Note:
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only
and functional operation of the device at these or any other condition beyond those indicated in the operational sections of the specifications is
not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
T
A
= 25°C, V
CC
= 2.7V ~ 5.5V, unless otherwise noted. Typical value are T
A
= +25°C, V
CC
= 3.6V.
Symbol
V
CC
I
CC
I
SD
I
IR
I
P
V
INT
L
V
IH
V
IL
Parameter
Supply voltage
Quiescent current
Shutdown current
Average current of IRLED
Peak current of IRLED
INTB pin output voltage low
Maximum detect distance
Input logic high voltage
Input logic low voltage
V
SDB
= V
CC
V
SDB
= 0V
V
LED
=3.6V(Note 1)
EC = “0001” (Note 1,2)
I
OL
= 4mA
EC = “0001” (Note 3)
V
CC
= 2.7V
V
CC
= 5.5V
1.4
15
0.4
Condition
Min.
2.7
0.6
1
0.8
400
0.2
3
Typ.
Max.
5.5
Unit
V
mA
μA
mA
mA
V
cm
V
V
DIGITAL INPUT SWITCHING CHARACTERISTICS (Note 1)
Symbol
f
SCL
t
BUF
t
HD, STA
t
SU, STA
t
SU, STO
t
HD, DAT
t
SU, DAT
t
LOW
t
HIGH
t
R
t
F
Parameter
Serial-Clock frequency
Bus free time between a STOP and a START
condition
Hold time (repeated) START condition
Repeated START condition setup time
STOP condition setup time
Data hold time
Data setup time
SCL clock low period
SCL clock high period
Rise time of both SDA and SCL signals,
receiving
Fall time of both SDA and SCL signals,
receiving
(Note 4)
(Note 4)
100
1.3
0.7
20+0.1Cb
20+0.1Cb
300
300
1.3
0.6
0.6
0.6
0.9
Condition
Min.
Typ.
Max.
400
Unit
kHz
μs
μs
μs
μs
μs
ns
μs
μs
ns
ns
Note 1:
Guaranteed by design.
Note 2:
The EC bit is used to set emitting current. Please refer to the detailed information in Page 7.
Note 3:
Because of different IRLED and material of cover, the detection distance will be different. The detail parameter should be tested.
IR26-21C/L110/CT for IRLED is recommended.
Note 4:
Cb = total capacitance of one bus line in pF. I
SINK
≤
6mA. t
R
and t
F
measured between 0.3 × V
CC
and 0.7 × V
CC
.
Integrated Silicon Solution, Inc. – www.issi.com
Rev. B, 07/04/2013
4
IS31SE5001
DETAILED DESCRIPTION
I2C INTERFACE
The IS31SE5001 uses a serial bus, which conforms to
the I2C protocol, to control the chip’s functions with two
wires: SCL and SDA. The IS31SE5001 has a 7-bit
slave address (A7:A1), followed by the R/W bit, A0. Set
A0 to “0” for a write command and set A0 to “1” for a
read command.
The complete slave address is:
Table 1 Slave Address (Write only):
Bit
Value
A7:A1
1010101
A0
1/0
After the last bit of the chip address is sent, the master
checks for the IS31SE5001’s acknowledge. The
master releases the SDA line high (through a pull-up
resistor). Then the master sends an SCL pulse. If the
IS31SE5001 has received the address correctly, then
it holds the SDA line low during the SCL pulse. If the
SDA line is not low, then the master should send a
“STOP” signal (discussed later) and abort the transfer.
Following acknowledge of IS31SE5001, the register
address byte is sent, most significant bit first.
IS31SE5001 must generate another acknowledge
indicating that the register address has been received.
Then 8-bit of data byte are sent next, most significant
bit first. Each data bit should be valid while the SCL
level is stable high. After the data byte is sent, the
IS31SE5001 must generate another acknowledge to
indicate that the data was received.
The “STOP” signal ends the transfer. To signal “STOP”,
the SDA signal goes high while the SCL signal is high.
READING PORT REGISTERS
To read the device data, the bus master must first send
the IS31SE5001 address with the R/W bit set to “0”,
followed by the command byte, which determines
which register is accessed. After a restart, the bus
master must then send the IS31SE5001 address with
the R/W bit set to “1”. Data from the register defined
by the command byte is then sent from the
IS31SE5001 to the master (Figure 5).
____
____
The SCL line is uni-directional. The SDA line is
bi-directional (open-collector) with a pull-up resistor
(typically 4.7kΩ). The maximum clock frequency
specified by the I2C standard is 400kHz. In this
discussion, the master is the microcontroller and the
slave is the IS31SE5001.
The timing diagram for the I2C is shown in Figure 2.
The SDA is latched in on the stable high level of the
SCL. When there is no interface activity, the SDA line
should be held high.
The “START” signal is generated by lowering the SDA
signal while the SCL signal is high. The start signal will
alert all devices attached to the I2C bus to check the
incoming address against their own chip address.
The 8-bit chip address is sent next, most significant bit
first. Each address bit must be stable while the SCL
玄铁RISC-V活动专区
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
