ispClock5312S Evaluation Board
User’s Guide
August 2007
Revision: EB32_01.0
Lattice Semiconductor
ispClock5312S Evaluation Board
User’s Guide
Introduction
The family of ispClock™5300S devices from Lattice Semiconductor Corporation provide in-system-programmable
zero delay universal fan-out buffers for use in clock distribution applications. Single-ended ultra low skew outputs
are organized with two outputs per bank. Each pair of outputs may be independently configured to support sepa-
rate I/O standards (LVTTL, LVCMOS -3.3V, 2.5V, 1.8, SSTL, HSTL) and output frequency. In addition, each output
provides independent programmable control of termination, slew-rate, and timing skew. All configuration informa-
tion is stored on chip in non-volatile E
2
CMOS
®
memory.
The ispClock5300S devices provide extremely low propagation delay (zero-delay) from input to output using the
on-chip low jitter high-performance phase locked loop (PLL). A set of three programmable 5-bit counters can be
used to generate three frequencies derived from the PLL clock. These counters are programmable in powers of 2
only (1, 2, 4, 8, 16, 32). The clock output from any of the V-dividers can then be routed to any clock output pair
through the output routing matrix. The output routing matrix also enables routing of reference clock inputs directly
to any output. For additional details, please refer to the ispPAC-CLK5300S Family Data Sheet.
Figure 1. ispClock5312S Evaluation Board
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Lattice Semiconductor
ispClock5312S Evaluation Board
User’s Guide
ispClock5312S Evaluation Board
The ispClock5312S is the first member of the ispClock5300S family with six output banks and thus has 12 single-
ended ultra low skew outputs. The ispClock5312S evaluation board features this device with full support circuitry for
power, programming, testing, and evaluation. The “A” output for each bank is supported with matched transmission
lines, optional on-board termination, and SMA connections at the edge of the board to provide full flexibility in mea-
surement and evaluation. Output 1B is hard-wired to the feedback input to complete the feedback loop of the PLL
because, the ispClock5300S family of devices only supports external feedback. Each output bank has separate
decoupling to isolate the outputs if they are configured for different frequencies. An on board 100 MHz oscillator
with 3.3V CMOS output is connected to the REFB input of the ispClock5312S. The REFA input is connected to an
SMA connector for testing with different input frequencies.
For a complete list of the various connections and interfaces used on the ispClock5312S evaluation board, please
refer to the schematics in the appendix of this document.
Finally, the ispClock5312S evaluation board is 100% lead free and ROHS compliant as Lattice Semiconductor Cor-
poration is sensitive to environmental issues.
Additional Resources
Additional resources relating to the ispClock5312S Evaluation Board are available on the Lattice web site. Go to:
www.latticesemi/boards and navigate to “mixed signal boards” to find the appropriate link. Updates to this docu-
ment can be found there, as well as sample programs and links to other related items.
PAC-Designer
®
PAC-Designer is the software used to develop custom programs for the ispClock5312S device, generate program-
ming files, and manage the download/programming of the device.
PAC-Designer is available for download from the Lattice web site at: www.latticesemi.com/pac-designer.
Programming Interface
JTAG programming is supported with the eight-pin connector J5 and either the USB download cable (HW-USBN-
2A) or the parallel download cable (HW-DLN-3C). The Windows-based program PAC-Designer provides an intuitive
interface for configuring the ispClock5312S and can be used to either directly program the evaluation board or to
export a JEDEC file which can be used with ispVM
®
to program the evaluation board.
ispVM system is available for download from the Lattice web site at: www.latticesemi.com/ispvm.
Important Note: The board must be un-powered when connecting, disconnecting, or reconnecting the ispDOWN-
LOAD
®
Cable. Always connect the ispDOWNLOAD Cable’s GND pin (black wire), before connecting any other
JTAG pins. Failure to follow these procedures can in result in damage to the ispClock5312S device and render the
board inoperable.
Demo Configuration and Reprogramming
The ispClock5312S evaluation board is preprogrammed at the factory with a demonstration configuration. This
demonstration configuration can be reprogrammed into the evaluation board from PAC-Designer by browsing the
library files as shown in Figure 2.
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Lattice Semiconductor
Figure 2. Demonstration File in PAC-Designer’s Library
ispClock5312S Evaluation Board
User’s Guide
Power Supply Considerations
All that is needed to power the ispClock5312S evaluation board is a 5V power supply capable of providing one
ampere or more. The board can be powered either by a wall adapter with a 2.5mm coaxial power plug at J3 or from
a bench supply with banana plugs at J1 and J2. Once onboard, the five volts is regulated (U1) to provide the 3.3V
supply needed for VCCD, VCCA, VCCJ, and VCCO for banks zero, one, and two.
A second adjustable regulator (U2) provides the VCCO for banks three, four, and five and it is programmable using
the on-board resistors and three of the DIP-switches of SW1. To bypass the on-board regulators, jumpers J4 and
J6 can be cut on the bottom of the board to allow external supplies to power the ispClock5312S.
Input/Output Connections
This board incorporates tapered transitions from the SMA connectors to the matched 50-ohms microstrip transmis-
sion lines. All of the output transmission lines are matched in length to the sense signals (REFA, REFB, and FEED-
BACK) to support accurate timing measurements both for bank-to-bank and input to output. The header at J8
provides access to the essential control and monitor signals of the ispClock5312S such as REFSEL,
PLL_BYPASS, OEX, OEY, LOCK, and RESET.
An off-board CMOS clock can be used by connecting to the REFA (J16) SMA connector. The ispClock5312S can
also be driven from an external differential clock source by moving the zero-ohm resistor from the R35 location to
the R37 location and connecting the clocks to both REFA and REFB inputs (J16 and J17). When an external clock
source is used, switches 1 and 2 of DIP-switch SW1 should be in the left position (OSC OFF and REFSEL A).
On-Board Termination
The ispClock5312S evaluation board is equipped with zero-ohm 0603 SMD resistors in series with the six outputs
and their corresponding SMA connectors in order to drive an off-board CMOS loads. This is shown in Figure 3-A.
However, these resistors can be replaced and additional resistors added to employ a variety of termination net-
works to match the desired output mode. In Figure 3-B the zero-ohm resistor is replaced with a 950-ohm sense
resistor and a load resistor is added to ground. The input impedance of the oscilloscope provides a 20:1 probe
attenuation. A small (5pF to 10pF) cap can be added on top of the load resistor to simulate a CMOS input. In Fig-
ure 3-C a divider network terminates the transmission line at 1/2 VCCO into a 50-ohm load and the 950-ohm resis-
tor allows sensing by the oscilloscope with a 20:1 probe attenuation. A low value capacitor (5pF to 10pF) can be
soldered on top of the 100-ohm resistor to ground to simulate an input to SSTL logic.
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Lattice Semiconductor
Figure 3. Onboard Output Termination Options
Bank
Output
0
SMA
ispClock5312S Evaluation Board
User’s Guide
A) As Shipped.
Oscilloscope
Bank
Output
950
SMA
R
L
50
B) CMOS Load.
20:1 Probe Attenuation.
VCCO
100
Bank
Output
100
950
SMA
Oscilloscope
C) SSTL Load.
20:1 Probe Attenuation.
50
The ispClock5312S evaluation board also supports input termination for the reference clock inputs and the feed-
back input if they are configured as SSTL. For CMOS operation (default) nothing needs to be added to the board.
For each SSTL input there is a set of pads on the backside of the board for a resistor and capacitor to terminate the
input as close to the device as possible. In addition, for SSTL termination pin 8 of the header J8 needs to be con-
nected to either pin 9 or 10 of the same header or connected off board to an adjustable supply to set the termina-
tion voltage. Note the voltage applied at pin 8 of J8 will be twice the termination voltage as U3 divides the input
voltage in half, see Figure 4 and the schematic in the appendix for more details.
Figure 4. Optional Input Termination for SSTL
REF_A,
REF_B,
FBK
2xVTT
J8-8
VCCO
INPUT
LP2995
U3
VTT
50
0.1uF
J8-9
J8-10
VCC
DIP Switch
To simplify the use of the ispClock5312S evaluation board an 8-position DIP switch (SW1) is provided for the more
common adjustments. The switch can roughly be divided into four sections; reference oscillator control, PLL con-
trol, output enables, and VCCO control. Table 1 lists the switches and their respective functions. Note that for switch
sections 6, 7, and 8 only one should be on at a time. The default setting with all the switches to the left (off) enables
the onboard oscillator, selects that as the clock reference, and allows the PLL to lock to that frequency.
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