DATASHEET
ISL6131, ISL6132
Multiple Voltage Supervisory ICs
The ISL6131 and ISL6132 are a family of high-accuracy,
multi-voltage supervisory ICs designed to monitor voltages
greater than 0.7V in applications ranging from
microprocessors to industrial power systems. The ISL6131 is
an undervoltage four-supply supervisor, and the ISL6132 is a
two-voltage supervisor monitoring for undervoltage (UV) and
overvoltage (OV) conditions.
Both ICs feature four external resistor programmable voltage
monitoring (VMON) inputs, each with a related STATUS output
that individually reports the related monitor input condition. In
addition, there is a Power-Good (PGOOD) signal that asserts
high when the STATUS outputs are in their correct state. A
stability delay of approximately 160ms ensures that the
monitored supply is stable before STATUS and PGOOD are
released to go high. The PGOOD and STATUS outputs are
open-drain to allow OR’ing of the signals and interfacing to a
wide range of logic levels.
STATUS and PGOOD outputs are guaranteed to be valid with IC
bias lower than 1V, eliminating concern about STATUS and
PGOOD outputs during IC bias up and down. VMON inputs are
designed to ignore momentary transients on the monitored
supplies.
FN9119
Rev 6.00
February 11, 2014
Features
• Operates from 1.5V to 5.5V Supply Voltage
• Four Adjustable Voltage Monitoring Thresholds
• 150ms STATUS/PGOOD Stability Time Delay
• Four Individual Open Drain STATUS Outputs
• Guaranteed STATUS/PGOOD Valid to V
DD
<1V
• V
DD
and VMON Glitch Immunity
• V
DD
Lock-Out
• 4mm X 4mm QFN Package
- Compliant to JEDEC PUB95 MO-220
QFN - Quad Flat No Leads - Package Outline
- Near Chip Scale Package footprint, which improves PCB
efficiency and has a thinner profile
• Pb-Free (RoHS Compliant)
Applications
• Multivoltage DSPs and Processors
• µP Voltage Monitoring
• Embedded Control Systems
• Graphics Cards
• Intelligent Instruments
• Medical Equipment
• Network Routers
• Portable Battery-Powered Equipment
• Set-Top Boxes
• Telecommunications Systems
UVSTATUS_1
OVSTATUS_1
UVSTATUS_2
STATUS D
STATUS C
STATUS B
STATUS A
OVSTATUS_2
V2 IN
D IN
C IN
B IN
A IN
V1 IN
Ru
Rm
Rl
V
DD
GROUND
V
DD
GROUND
PGOOD1
PGOOD2
EN1 EN2
VMON_A
VMON_B
VMON_C
VMON_D
UVMON_1
UVMON_2
OVMON_1
OVMON_2
PGOOD
EN
FIGURE 1. ISL6131 TYPICAL APPLICATION USAGE
FIGURE 2. ISL6132 TYPICAL APPLICATION USAGE
FN9119 Rev 6.00
February 11, 2014
Page 1 of 15
ISL6131, ISL6132
Ordering Information
PART
NUMBER
(Notes 2, 3)
ISL6131IRZA
(Note 1)
ISL6132IRZA
(Note 1)
ISL6131EVAL1Z
ISL6132EVAL1Z
NOTES:
1. Add “-T*” suffix for tape and reel. Please refer to
TB347
for details on
reel specifications.
2. These Intersil Pb-free plastic packaged products employ special
Pb-free material sets, molding compounds/die attach materials, and
100% matte tin plate plus anneal (e3 termination finish, which is
RoHS compliant and compatible with both SnPb and Pb-free
soldering operations). Intersil Pb-free products are MSL classified at
Pb-free peak reflow temperatures that meet or exceed the Pb-free
requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information
page for
ISL6131, ISL6132.
For more information on MSL, please see
Tech Brief
TB363.
PART
MARKING
61 31IRZ
61 32IRZ
TEMP.
RANGE
(°C)
-40 to +85
-40 to +85
PACKAGE
(Pb-free)
24 Ld 4x4 QFN
24 Ld 4x4 QFN
PKG.
DWG. #
L24.4x4
Pin Configuration
ISL6131, ISL6132
(24 LD QFN)
TOP VIEW
24
1
23
22
21
20
19
18
17
16
PD
4
5
6
7
8
9
10
11
12
15
14
13
L24.4x4
2
3
Evaluation Board
Evaluation Board
Pin Descriptions
PIN
6131
23
10
20
12
17
14
NA
NA
NA
NA
24
6132
23
10
NA
NA
NA
NA
12
20
17
14
24
PIN NAME
V
DD
GND
VMON_A
VMON_B
VMON_C
VMON_D
OVMON_1
UVMON_1
UVMON_2
OVMON_2
PGOOD
On the ISL6131, PGOOD is the Boolean AND function of all four STATUS outputs.
On the ISL6132, PGOOD is for the AB pair and signals high when the monitored voltage is within the specified window
and the A and B STATUS output states are correct.
This is an open-drain output and is to be pulled high to the appropriate level with an external resistor to a V
DD
maximum level.
PGOOD2 is for the CD pair and signals high when the monitored voltage is within the specified window and when the
C and D STATUS output states are correct.
This is an open-drain output and is to be pulled high to the appropriate level with an external resistor to a V
DD
maximum level.
Bias IC from nominal 1.5V to 5V
IC ground
On the ISL6131, these inputs provide a programmable UV threshold referenced to an internal 0.633V. The related
STATUS output asserts when the related input > internal reference voltage.
On the ISL6132, these inputs provide a programmable UV and OV threshold referenced to an internal 0.633V
reference. In the ‘AB’ pair, VMON_A is the UV input, and VMON_B is the OV input. In the ‘CD’ pair, VMON_C is the UV
input, and VMON_D is the OV input.
These inputs have a 30µs glitch filter to prevent PGOOD reset caused by a transient.
FUNCTION DESCRIPTION
NA
9
PGOOD2
FN9119 Rev 6.00
February 11, 2014
Page 2 of 15
ISL6131, ISL6132
Pin Descriptions
PIN
6131
2
5
6
7
NA
NA
NA
NA
1
NA
-
NC
6132
NA
NA
NA
NA
5
2
6
7
1
11
-
PIN NAME
STATUS_A
STATUS_B
STATUS_C
STATUS_D
OVSTATUS_1
UVSTATUS_1
UVSTATUS_2
OVSTATUS_2
EN1
EN2
PD
(Continued)
FUNCTION DESCRIPTION
On the ISL6131, each STATUS provides a high signal through pull-up resistors about 160ms after its related VMON
has continuously been > Vuv_vth. This delay is for stabilization of monitored voltages. STATUS de-asserts and pulls
low upon VMON not being satisfied for about 30µs.
On the ISL6132, the STATUS outputs indicate compliance with a high output state for each pair of monitors.
On the ISL6131, this pin provides four voltage UV functions for enabling/disabling input. Internally pulled up to V
DD
.
Controls monitor 1 (AB pair) on ISL6132.
On the ISL6132, this pin controls monitor 2 (CD pair) voltage and voltage monitoring function enabling input; pulled
up to V
DD
.
Thermal Pad. Should be electrically connected to GND.
No Connect
3, 4, 8, 13, 15, 16, 18,
19, 21, 22
FN9119 Rev 6.00
February 11, 2014
Page 3 of 15
ISL6131, ISL6132
Absolute Maximum Ratings
V
DD
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +6.0V
VMON, ENABLE, STATUS, PGOOD . . . . . . . . . . . . . . . . . . . -0.3V to V
DD
+0.3V
ESD Classification. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2kV (HBM)
Thermal Information
Thermal Resistance (Typical, Notes 4, 5)
JA
(°C/W)
JC
(°C/W)
4x4 QFN Package. . . . . . . . . . . . . . . . . . . . .
48
9
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . .+150°C
Maximum Storage Temperature Range . . . . . . . . . . . . . .-65°C to +150°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Operating Conditions
V
DD
Supply Voltage Range . . . . . . . . . . . . . . . . . . . . . . . . . . .+1.5V to +5.5V
Temperature Range (
T
A
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
4.
JA
is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief
TB379
for details.
5. For
JC
, the “case temp” location is the center of the exposed metal pad on the package underside.
6. All voltages are relative to GND, unless otherwise specified.
Electrical Specifications
Nominal V
DD
= 1.5V to +5V, T
A
= T
J
= -40°C to +85°C, unless otherwise specified.
Boldface limits apply
over the operating temperature range, -40°C to +85°C.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
(Note 7)
TYP
MAX
(Note 7)
UNIT
VMON/ENABLE INPUTS
VMON Falling Threshold
VMON Threshold Temp. Coeff.
VMON Hysteresis
VMON Glitch Filter
VMON Minimum Input Impedance
ENABLE L2H, Delay to STATUS & PGOOD
EN H2L, Delay to PGOOD
EN H2L, Delay to STATUS
ENABLE Pull-up Voltage
ENABLE Threshold Voltage
V
ENVTH
V
VMONvth
TC
VMONvth
V
VMONhys
Tfil
Zin_min
T
J
= +40°
C, VMON within 63mV of
V
VMONvth
VMON valid, EN high to STATUS and PG high
EN low to PGOOD low
EN low to STATUS low
EN open
-
-
-
-
-
T
J
= +25°
C
T
J
from -40°
C
to +85°
C
619
-
-
-
633
40
10
30
8
160
-
13
V
DD
V
DD
/2
-
0.1
-
-
-
647
-
-
-
mV
V/°
C
mV
s
M
ms
s
s
V
V
STATUS/PGOOD OUTPUTS
STATUS Pull-Down Current
STATUS/PGOOD Delay after VMON Valid
STATUS/PGOOD Output Low
I
RSTpd
T
delST
Vol
RST
= 0.1V
VMON > V
UVvth
to STATUS = 0.2V
-
-
-
88
160
0.04
-
-
0.1
mA
ms
V
Measured at V
DD
= 1.0V
BIAS
IC Supply Current
IC Supply Current
IC Supply Current
V
DD
Power On
V
DD
Power On Lock Out
I
VDD_5.5V
I
VDD_3.3V
I
VDD_1.5V
V
DD
_POR
V
DD
_LO
V
DD
= 5V
V
DD
= 3.3V
V
DD
= 1.5V
V
DD
high to low
V
DD
low to high
-
-
-
-
-
170
145
100
0.89
0.91
-
-
-
1
-
A
A
A
V
V
NOTE:
7. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested.
FN9119 Rev 6.00
February 11, 2014
Page 4 of 15
ISL6131, ISL6132
Description and Operation
The ISL6131 is a four-voltage, high-accuracy, supervisory IC
designed to monitor multiple voltages greater than 0.7V relative
to Pin 10 of the IC.
Upon V
DD
bias power-up, the STATUS and PGOOD outputs are
held correctly low once V
DD
is as low as 1V. Once biased to 1.5V,
the IC continuously monitors from one to four voltages
independently through external resistor dividers, comparing each
voltage monitoring (VMON) pin voltage to an internal 0.633V
(V
VMONvth
) reference.
With the EN input driven high or open, as each VMON input rises
above V
VMONvth
, a timer is set to ensure ~160ms of continuous
compliance. Then the related STATUS output is released to be
pulled high. The STATUS outputs are open-drain to allow OR’ing of
these signals and interfacing to a logic high level up to V
DD
. The
STATUS outputs are designed to reject short transients (~30s)
on the VMON inputs. Once all STATUS outputs are high, a
Power-Good (PGOOD) output signal is generated high to indicate
that all monitored voltages are greater than minimum
compliance level.
Once any VMON input falls below V
VMONvth
for longer than the
glitch filter time, both the PGOOD and the related STATUS output
are pulled low. The other STATUS outputs remain high as long as
their corresponding VMON voltage remains valid and the PGOOD
validation process is reset.
Figure 1 shows the ISL6131 typical application schematic, and
Figure 3 is an operational timing diagram. See Figures 10 to 17 for
ISL6131 function and performance. Figures 10 and 11 show the
V
DD
rising along with STATUS and PGOOD response. Figures 12
and 13 illustrate VMON falling below V
VMONvth
, and Figure 14
shows VMON rising above V
VMONvth
with STATUS and PGOOD
response. Figure 15 shows V
DD
failing, with STATUS and PGOOD
response. Figures 16 and 17 show ENABLE to STATUS and PGOOD
timing.
If less than four voltages are being monitored, connect the
unused VMON pins to V
DD
for proper operation. All unused
STATUS outputs can be left open.
The ISL6132 is a dual voltage monitor for undervoltage and
overvoltage compliance. Figure 2 shows the typical ISL6132
implementation schematic, and Figure 4 is the operational timing
diagram.
There are two pairs of monitors, each with an undervoltage
(UVMON) input and an overvoltage (OVMON) input, along with
associated STATUS and PGOOD outputs.
Upon V
DD
bias power-up, the STATUS and PGOOD outputs are
held correctly low, once V
DD
is as low as 1V. Once biased to 1.5V,
the IC continuously monitors the voltage through external resistor
dividers, comparing each VMON pin voltage to an internal 0.633V
reference. At proper bias, OVSTATUS is pulled high, and
UVSTATUS and PGOOD are pulled low. Once the UVMON
input > VMON Vth continuously for ~160ms, its associated
STATUS output releases high, indicating that the minimum
voltage condition has been met. As both UVMON and OVMON
inputs are satisfied, the PGOOD output is released to go high,
indicating that the monitored voltage is within the specified
window. Figure 18 shows this performance for a 4V to 5V
window.
When VMON does not satisfy its voltage high or low criteria for
more than the glitch filter time, the associated STATUS and
PGOOD are pulled low. Figures 19 and 20 show this performance
for a 4V to 5V compliant window.
Figures 21 through 23 show the VMON glitch filter timing to
STATUS and PGOOD notification and transient immunity.
The ENABLE input, when pulled low, allows the monitoring and
reporting functions to be disabled. Figure 24 shows ENABLE high
to PGOOD timing for compliant voltage.
When choosing resistors for the divider, remember to keep the
current through the string bounded by power loss tolerance at the
top end and noise immunity at the bottom end. For most
applications, total divider resistance in the 10k -100krange
is advisable, with 1% tolerance resistors being used to reduce
monitoring error.
Figures 1 and 2 show that choosing the two resistor values is
straightforward for the ISL6131, because the ratio of resistance
should equal the ratio of the desired trip voltage to the internal
reference, 0.633V.
For the ISL6132, two dividers of two resistors each can be
employed to monitor the OV and UV levels for each voltage.
Otherwise, use a single three-resistor string for each voltage. In
the three-resistor divider string, the ratio of the desired
overvoltage trip point to the internal reference is equal to the
ratio of the two upper resistors to the lowest (GND connected)
resistor. The desired undervoltage trip point ratio to the internal
reference voltage is equal to the ratio of the uppermost (voltage
connected) resistor to the two lower resistors, as shown in the
following example:
1. Establish lower and upper trip level: 3.3V ±20% or 2.64V (UV)
and 3.96V (OV)
2. Establish total resistor string value: 10kIr = divider current
3. (Rm + Rl) * Ir = 0.623V @ UV and Rl * Ir = 0.633V @ OV
4. Rm + Rl = 0.623V/Ir @ UV => Rm + Rl =
0.623V/(2.64V/10kΩ) = 2.359kΩ
5. Rl = 0.633V/Ir @ OV => Rl = 0.633V/(3.96V/10kΩ) = 1.598kΩ
6. Rm = 2.359kΩ - 1.598kΩ = 0.761kΩ
7. Ru = 10kΩ - 2.397kΩ = 7.641kΩ
Choose standard value resistors that most closely approximate
these ideal values. Choosing a different total divider resistance
value may yield a more ideal ratio with available resistors values.
FN9119 Rev 6.00
February 11, 2014
Page 5 of 15
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