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ISL70002SEHVF: 产品描述Switching Voltage Regulators RADIATION HARDENED 12A SYNCHRONOUS BUCK REGULATOR, CLASS V,; 产品类别电源/电源管理电源电路; 文件大小583KB，共25页; 制造商Renesas(瑞萨电子); 官网地址https://www.renesas.com/; 标准

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ISL70002SEHVF概述

Switching Voltage Regulators RADIATION HARDENED 12A SYNCHRONOUS BUCK REGULATOR, CLASS V,

ISL70002SEHVF规格参数

参数名称	属性值
是否Rohs认证	符合
厂商名称	Renesas(瑞萨电子)
零件包装代码	QFP
包装说明	QFF, QFL64,.55SQ,25
针数	64
Reach Compliance Code	compliant
ECCN代码	USML XV(E)
其他特性	ADJUSTABLE MODE FROM 0.8 TO 4.675
模拟集成电路 - 其他类型	SWITCHING REGULATOR
控制模式	CURRENT-MODE
控制技术	PULSE WIDTH MODULATION
最大输入电压	5.5 V
最小输入电压	3 V
标称输入电压	3.3 V
JESD-30 代码	S-CQFP-F64
长度	14.15 mm
功能数量	1
端子数量	64
最高工作温度	125 °C
最低工作温度	-55 °C
最大输出电流	1.2 A
标称输出电压	1.8 V
封装主体材料	CERAMIC, METAL-SEALED COFIRED
封装代码	QFF
封装等效代码	QFL64,.55SQ,25
封装形状	SQUARE
封装形式	FLATPACK
峰值回流温度（摄氏度）	NOT SPECIFIED
认证状态	Not Qualified
筛选级别	38535V;38534K;883S
座面最大高度	2.67 mm
表面贴装	YES
切换器配置	BUCK
最大切换频率	1200 kHz
温度等级	MILITARY
端子形式	FLAT
端子节距	0.635 mm
端子位置	QUAD
处于峰值回流温度下的最长时间	NOT SPECIFIED
宽度	14.15 mm

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DATASHEET

ISL70002SEH

Radiation Hardened and SEE Hardened 12A Synchronous Buck Regulator with

Current Sharing

The

ISL70002SEH

is a radiation hardened and SEE hardened

high efficiency monolithic synchronous buck regulator with

integrated MOSFETs. This single chip power solution operates

over an input voltage range of 3V to 5.5V and provides a

tightly regulated output voltage that is externally adjustable

from 0.8V to ~85% of the input voltage. Output load current

capacity is 12A for T

≤

+150°C. The two ISL70002SEH

devices configured to current share can provide 19A total

output current, assuming ±27% worst-case current share

accuracy.

The ISL70002SEH utilizes peak current-mode control with

integrated error amp compensation and pin selectable slope

compensation. Switching frequency is also pin selectable to

either 1MHz or 500kHz. Two devices can be synchronized

180° out-of-phase to reduce input RMS ripple current.

High integration makes the ISL70002SEH an ideal choice to

power small form factor applications. Two devices can be

synchronized to provide a complete power solution for large

scale digital ICs, like field programmable gate arrays (FPGAs)

that require separate core and I/O voltages.

FN8264

Rev 8.00

October 1, 2015

Features

• DLA SMD

5962-12202

• Output current for a single device

- 14A at T

= +125

C; 12A at T

= +150

• Output current for two paralleled devices

- 22A at T

= +125

C; 19A at T

= +150

• Available in a thermally enhanced heatsink package - R64.C

• 1MHz or 500kHz switching frequency

• 3V to 5.5V supply voltage range

• ±1% Reference voltage (line, load, temp. and rad)

• Prebiased load compatible

• Redundancy/junction isolation: Exceptional SET

performance

• Excellent transient response

• High efficiency >90%

• Two ISL70002SEH synchronization, inverted-phase

• Comparator input for enable and power-good

• Input undervoltage, output undervoltage and adjustable

output overcurrent protection

• QML qualified per MIL-PRF-38535

• Full military temperature range operation (-55

C to +125

• Radiation environment

- High dose . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100krad(Si)

- ELDRS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100krad(Si)*

*Level guaranteed by characterization; “EH” version is

production tested to 50krad(Si).

• SEE hardness

- SEL and SEB LET

. . . . . . . . . . . . . . . . 86.4MeV/mg/cm

- SEFI LET

. . . . . . . . . . . . . . . . . . . . . . . . . . 43MeV/mg/cm

- SET LET

. . . . . . . . . . . . . . . . . . . . . . . . 86.4MeV/mg/cm

Applications

• FPGA, CPLD, DSP, CPU core and I/O voltages

• Low-voltage, high-density distributed power systems

Related Literature

•

AN1732

“ISL70002SEH 12A Synchronous Buck Regulator

Evaluation Board User Guide”

•

AN1953

“ISL70002SEH Dual Phase Current Share

Evaluation Board User Guide”

100

EFFICIENCY (%)

AMPLITUDE (V)

LOAD CURRENT (A)

1.2V

1.5V

1.8V

2.5V

3.3V

CH2 SLAVE LX + 15V

CH1 MASTER LX + 20V

CH3 VOUT x 10

CH4 SYNC

10 11 12

-6

-4

-2

FIGURE 1. EFFICIENCY 5V INPUT, 500kHz, T

case

= +25°C

FIGURE 2. 2-PHASE SET PERFORMANCE at 86.4MeV/mg/cm

FN8264 Rev 8.00

October 1, 2015

Page 1 of 25

ISL70002SEH

Pin Descriptions

R64.A

R64.C

PIN NUMBER PIN NUMBER PIN NAME

DESCRIPTION

This pin is the voltage feedback input to the internal error amplifier. Connect a resistor from FB to VOUT and

from FB to AGND to adjust the output voltage in accordance with

Equation 1:

OUT

REF

 





 

(EQ. 1)

Where:

OUT

= Output voltage

REF

= Reference voltage (0.6V typical)

= Top divider resistor (Must be 1kΩ

= Bottom divider resistor

The top divider resistor must be 1kΩ to mitigate SEE. Connect a 4.7nF ceramic capacitor across R

to mitigate

SEE and to improve stability margins.

If using current share, tie FB of the master to FB of the slave.

2, 4, 6

ISHA,

If configured as a current share master (ISHSL = DGND, ISHEN = DVDD), the ISHA/ISHB/ISHC pins are outputs

ISHB, ISHC that provide a current equal to 25 times the redundant A/B/C error amp output currents plus

ISHREFA/ISHREFB/ISHREFC (nominally 100µA each). If configured as a current share slave (ISHSL = DVDD,

ISHEN = DVDD), the ISHA/ISHB/ISHC pins are inputs that become the slave’s redundant A/B/C error amp

output current. If using current share, tie ISHA/ISHB/ISHC of the master to ISHA/ ISHB/ ISHC of the slave. If

not using current share, tie ISHA/ISHB/ISHC to DVDD. ISHA/ISHB/ISHC are tri-stated prior to a valid POR and

when ISHEN = DGND.

ISHREFA,

ISHREFB,

ISHREFC

If configured as a current share master (ISHSL = DGND, ISHEN = DVDD), the ISHREFA/ISHREFB/ISHREFC pins

provide a reference output current equal to 100µA each. If configured as a current share slave (ISHSL = DVDD,

ISHEN = DVDD), the ISHREFA/ISHREFB/ISHREFC pins accept a reference input current. For a current share

slave, this input current is used together with the ISHA/ISHB/ISHC current to determine the master’s

redundant A/B/C error amp output current. If using current share, tie ISHREFA/ISHREFB/ISHREFC of the

MASTER to ISHREFA/ISHREFB/ISHREFC of the slave. If not using current share, tie ISHREFA/ISHREFB/

ISHREFC to DVDD. The purpose of the reference current is to reduce the impact of external noise coupling onto

ISHA/ISHB/ISHC. ISHREFA/ISHREFB/ISHREFC are tri-stated prior to a valid POR and when ISHEN = DGND.

This pin is the bias supply input to the internal analog control circuitry. Locally filter this pin to AGND using a

1Ω resistor and a 1µF ceramic capacitor. Locate both filter components as close as possible to the IC. AVDD

should be the same voltage as DVDD and PVINx (±200mV).

This pin is the analog ground associated with the internal analog control circuitry. Connect this pin directly to

the PCB ground plane.

This pin is the digital ground associated with the internal digital control circuitry. Connect this pin directly to

the PCB ground plane.

This pin is the bias supply input to the internal digital control circuitry. Locally filter this pin to DGND using a

1Ω resistor and a 1µF ceramic capacitor. Locate both filter components as close as possible to the IC. DVDD

should be the same voltage as AVDD and PVINx (±200mV).

This pin is the soft-start input. Connect a ceramic capacitor from this pin to DGND to set the soft-start output

ramp time in accordance with

Equation 2:



REF



(EQ. 2)

3, 5, 7

AVDD

AGND

DGND

DVDD

Where:

= Soft-start output ramp time

= Soft-start capacitor

REF

= Reference voltage (0.6V typical)

= Soft-start charging current (23µA typical)

Soft-start time is adjustable from approximately 2ms to 200ms.

The range of the soft-start capacitor should be 82nF to 8.2µF, inclusive.

If using current share, C

of the slave should be at least twice the C

of the master.

PGOOD

This pin is the power-good output. This pin is an open drain logic output that is pulled to DGND when the output

voltage is outside a ±11% typical regulation window. This pin can be pulled up to any voltage from 0V to 5.5V,

independent of the supply voltage. A nominal 1kΩ to 10kΩ pull-up resistor is recommended. Bypass this pin

to DGND with a 10nF ceramic capacitor to mitigate SEE. If using current share, tie PGOOD of the master to

PGOOD of the slave.

FN8264 Rev 8.00

October 1, 2015

Page 4 of 25

ISL70002SEH

Pin Descriptions

(Continued)

R64.A

R64.C

PIN NUMBER PIN NUMBER PIN NAME

ISHCOM

DESCRIPTION

ISHCOM is a bidirectional communication line between a current share master and a current share slave. If

using current share, tie ISHCOM of the master to ISHCOM of the slave. The master enables the slave by

resistively (~ 8.5kΩ) pulling ISHCOM high. The slave indicates an overcurrent fault condition to the master by

pulling ISHCOM low. To mitigate SET, connect a 47pF ceramic capacitor from ISHCOM to the PCB ground plane.

If not using current share this pin should be floated or connected to the PCB ground plane. ISHCOM is tri-stated

if ISHEN is low.

This pin is a logic input that is used to configure the IC as a current share master or slave. Tie this pin to DVDD

to configure the IC as a current share slave. Tie this pin to the PCB ground plane to configure the IC as a current

share master, or if the current share feature is not being used.

This pin is an input that enables/disables the current share feature. To enable the current share feature, tie

this pin to DVDD. To disable the current share feature, tie this pin to the PCB ground plane.

This pin is the input for selecting the rising and falling POR (Power-On-Reset) thresholds. For a nominal 5V

supply, connect this pin to DVDD. For a nominal 3.3V supply, connect this pin to DGND. For nominal supply

voltages between 5V and 3.3V, connect this pin to DGND.

This pin is the test data output of the internal BIT circuitry. Connect this pin to the PCB ground plane.

This pin is the test data input of the internal BIT circuitry. Connect this pin to the PCB ground plane.

This pin is a trim input and is used to adjust various internal circuitry. Connect this pin to the PCB ground plane.

This pin is connected to an internal metal die trace that serves as a sensitive node noise shield. Connect this

pin to the PCB ground plane.

When SYNC is configured as an output (clock Master Mode, M/S = DVDD), this pin drives the SYNC input of

another ISL70002SEH with a square ware that is inverted (~180° out-of-phase) from the master clockdriving

the master PWM circuits. When configured as an input (clock Slave Mode, M/S = DGND), this pin uses the

SYNC output from another ISL70002SEH or an external clock to drive the clock slave PWM circuitry. If

synchronizing to an external clock, the clock must be SEE hardened and the frequency must be within the

range of 400kHz to 1.2MHz.

These pins are the power supply inputs to the corresponding internal power blocks. These pins must be

connected to a common power supply rail, which must fall in the range of 3V to 5.5V. Bypass these pins directly

to PGNDx with ceramic capacitors located as close as possible to the IC. PVINx should be the same voltage as

DVDD and AVDD (±200mV).

These pins are the outputs of the corresponding internal power blocks and should be connected to the output

filter inductor. Internally, these pins are connected to the synchronous MOSFET power switches.

These pins are the power grounds associated with the corresponding internal power blocks. These pins also

provide the ground path for the metal package lid. Connect these pins directly to the PCB ground plane. These

pins should also connect to the negative terminals of the input and output capacitors. Locate the input and

output capacitors as close as possible to the IC.

This pin is the clock master/slave input for selecting the direction of the bidirectional SYNC pin. For

SYNC = Output (Master Mode), connect this pin to DVDD. For SYNC = Input (Slave Mode), connect this pin to

the PCB ground plane.

This pin is the oscillator frequency select input. Tie this pin to DVDD to select a 1MHz nominal oscillator

frequency. Tie this pin to the PCB ground plane to select a 500kHz nominal oscillator frequency.

These are No Connect pins that are not connected to anything internally. They should be connected to the PCB

ground plane.

For the R64.C package (heatsink option) this pin is electrically connected to the heatsink on the underside of

the package. Connect this pin and/or the heatsink to a thermal plane.

ISHSL

ISHEN

PORSEL

TDO

TDI

TPGM

GND

SYNC

23, 28, 32, 37, 38, 43, 44,

49, 53, 58

PVINx

24, 27, 33, 36, 39, 42, 45,

48, 54, 57

25, 26, 34, 35, 40, 41, 46,

47, 55, 56

LXx

PGNDx

M/S

31, 50

N/A

FSEL

NC, HS

FN8264 Rev 8.00

October 1, 2015

Page 5 of 25

ISL70002SEHVF

ISL70002SEHVF在线购买

ISL70002SEHVF概述

ISL70002SEHVF规格参数

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