19-4015; Rev 1; 12/06
MAX19586/MAX19588 Evaluation Kits
General Description
The MAX19586/MAX19588 evaluation kits (EV kits) are
fully assembled and tested PCBs that contain all the
components necessary to evaluate the performance of
the MAX19586 and MAX19588. The MAX19586 is a
16-bit, 80Msps analog-to-digital converter (ADC), while
the MAX19588 is a 16-bit, 100Msps ADC. The
MAX19586/MAX19588 EV kits can accept a differential
or single-ended analog input. For applications with a
single-ended signal source, the MAX19586/MAX19588
EV kits feature an on-board transformer that converts
this signal to the required differential signal. The digital
outputs produced by the MAX19586/MAX19588 can be
captured with a logic analyzer or data-acquisition sys-
tem. The EV kits operate from a 3.3V and a 1.8V power
supply.
Features
♦
Fully Assembled and Tested
♦
Up to 80Msps/100Msps Sampling Rate
♦
Single-Ended-to-Differential Clock Conversion
Circuitry
♦
Configurable for Differential or Single-Ended
Analog Input Signals
♦
On-Board Digital Output Buffer
♦
Low-Voltage and Low-Power Operation
♦
Simplifies Evaluation of the MAX19586/MAX19588
Evaluate: MAX19586/MAX19588
Part Selection Table
PART NUMBER
MAX19586ETN+
MAX19588ETN+
BITS
16
SPEED (Msps)
80
100
PART
MAX19586EVKIT+
MAX19588EVKIT+
Ordering Information
TEMP RANGE
0°C to +70°C*
0°C to +70°C*
IC PACKAGE
56 Thin QFN-EP**
56 Thin QFN-EP**
+Denotes
a lead-free and RoHS-compliant EV kit.
*This
limited temperature range is for the EV kit PCB only.
The MAX19586MAX19588 IC temperature range is -40°C
to +85°C.
**EP
= Exposed paddle.
Component List
DESIGNATION
C1, C6, C10,
C18, C28–C33
C2–C5, C8,
C9, C11, C12
C13, C14
QTY
10
DESCRIPTION
0.1µF ±10%, 50V X7R ceramic
capacitors (0603)
TDK C1608X7R1H104K
Not installed capacitors (0603)
1µF ±10%, 16V X5R ceramic
capacitors (0603)
TDK C1608X5R1C105K
C37
C19, C22, C25
3
220µF ±20%, 6.3V low-ESR tantalum
capacitors (D-case)
AVX TPSD227M006R0100
47µF ±20%, 6.3V X5R ceramic
capacitors (1210)
TDK C3225X5R0J476M
2.2µF ±20%, 6.3V X5R ceramic
capacitors (0603)
TDK C1608X5R0J225M
D1
CLOCK, INPUT+
INPUT-
J1, J2
J3, J4
1
2
0
2
2
1
DESIGNATION
C34, C38,
C39, C40
QTY
4
DESCRIPTION
0.01µF ±10%, 16V X7R ceramic
capacitors (0306)
TDK C0816X7R1C103K
0.1µF ±20%, 16V X7R ceramic
capacitors (0306)
TDK C0816X7R1C104M
0.1µF ±10%, 6.3V X5R ceramic
capacitor (0201)
TDK C0603X5R0J104K
Murata GRM33R60J104K
15mA, 70V, dual Schottky diode (SOT23)
Diodes Inc. BAS70-04 or
Central Semiconductor CMPD6263S
SMA PC mount connectors
Not installed SMA PC mount connector
2-pin headers
2 x 8-pin headers
0
C35, C36, C41,
C42, C43
5
2
C20, C23, C26
3
C21, C24, C27
3
________________________________________________________________
Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
MAX19586/MAX19588 Evaluation Kits
Evaluate: MAX19586/MAX19588
Component List (continued)
DESIGNATION
J5
J6
L1, L2, L3
L4
R1–R5, R8,
R9, R13
R6, R7,
R10, R11
R12
R14
R15
RA1, RA2
QTY
1
1
3
0
0
4
1
1
1
2
DESCRIPTION
2 x 20-pin header
PCB pin strip, 6 pins, 5mm pitch,
250V, 10A
EMI filters (1806)
Murata NFM41PC204F1H3B
Not installed, high-Q chip inductor
(0603)
Not installed, resistors (0603)
49.9Ω ±1% resistors (0603)
10kΩ ±1% resistor (0603)
120Ω ±5% resistor (0603)
49.9Ω ±1% resistor (0402)
120Ω ±5% resistor arrays
Panasonic EXB-2HV-121J
—
—
1
1
DESIGNATION
T1, T3
T2
U1
QTY
2
1
1
DESCRIPTION
1:2 RF transformers
Mini-Circuits ADT2-1T+
1:1 RF transformer
Mini-Circuits T1-1T-KK81+
See the
EV Kit-Specific Component
List
section
Low-voltage, 22-bit register
(64-pin TSSOP)
Fairchild 74VCX16722MTD
TinyLogic ULP-A inverter with
Schmitt trigger input (SC70-5)
Fairchild NC7SV14P5X
PC board terminal block (plug onto the
J6 pin strip) 6 pins, 5mm pitch, 250V, 10A
PCB: MAX19586/MAX19588
evaluation kits+
U2
1
U3
1
EV Kit-Specific Component List
EV KIT PART NUMBER
MAX19586EVKIT+
MAX19588EVKIT+
REFERENCE
DESIGNATOR
U1
DESCRIPTION
MAX19586ETN+ (56-pin, 8mm x 8mm x 0.8mm Thin QFN-EP**)
MAX19588ETN+ (56-pin, 8mm x 8mm x 0.8mm Thin QFN-EP**)
**EP
= Exposed paddle.
Component Suppliers
SUPPLIER
AVX Corp.
Central Semiconductor Corp.
Diodes Inc.
Fairchild Semiconductor
Mini-Circuits
Murata Mfg. Co., Ltd.
Panasonic Corp.
PHONE
843-946-0238
631-435-1110
805-446-4800
888-522-5372
718-934-4500
770-436-1300
714-373-7366
WEBSITE
www.avxcorp.com
www.centralsemi.com
www.diodes.com
www.fairchildsemi.com
www.minicircuits.com
www.murata.com
www.panasonic.com
TDK Corp.
847-803-6100
www.component.tdk.com
Note:
Indicate that you are using the MAX19586/MAX19588 when contacting these component suppliers.
2
_______________________________________________________________________________________
MAX19586/MAX19588 Evaluation Kits
Quick Start
Recommended Equipment
• DC power supplies:
Analog (AVDD)
Digital (DVDD)
Logic (VL)
3.3V, 500mA
1.8V, 100mA
1.8V, 100mA
4) Connect the output of the analog bandpass filter to
the INPUT+ SMA connector on the EV kit.
5) Connect header J5 to the HP/Agilent logic analyz-
er. Alternatively, for Tektronix-type logic analyzers,
connect to headers J1, J3, and J4. To capture the
DOR bit (data over-range), connect a free logic
analyzer data line to header J2. See the
Digital
Output Signals
section in this document for bit
locations and all header designations.
6) Connect the 3.3V, 500mA power supply to the
AVDD terminal. Connect the ground terminal of this
supply to the GND terminal.
7) Connect a 1.8V, 100mA power supply to the DVDD
terminal. Connect the ground terminal of this sup-
ply to the GND terminal.
8) Connect another 1.8V, 100mA power supply to the
VL terminal. Connect the ground terminal of this
supply to the corresponding GND terminal.
9) Turn on the power supplies.
10) Enable the signal generators. Set the clock signal
generator output power to +19dBm and the fre-
quency (f
CLK
) to 80MHz for the MAX19586 EV kit,
or 100MHz for the MAX19588 EV kit. Set the analog
input signal generator output to the desired fre-
quency and amplitude. For coherent data capture,
the signal generators should be phase-locked.
Adjust the analog input signal level to overcome
cable and filter losses that may exist in the signal’s
input path. Note that the ADC full scale is
+9.1dBm.
11) Enable the logic analyzer and start collecting data.
Evaluate: MAX19586/MAX19588
• Signal generator with low phase noise and low jitter
for clock input (e.g., HP/Agilent 8644B)
• Signal generator for analog signal input (e.g.,
HP/Agilent 8644B)
• Analog bandpass filters for input signal and clock
signal (e.g., Allen Avionics, K&L Microwave)
• Logic analyzer or data-acquisition system (e.g., HP/
Agilent 16500C, Tektronix TLA621)
Note: The
Quick Start
procedure in this section
only provides a quick functional check for the
MAX19586/MAX19588 EV kits. To verify the full
dynamic performance of the MAX19586/MAX19588,
refer to the
Testing the MAX1958_
sections in the
respective IC data sheets.
Procedure
The MAX19586/MAX19588 EV kits are fully assembled
and tested PCBs. Follow the steps below to verify
board operation (Figure 1).
Caution: Do not turn on
power supplies or enable signal generators until all
connections are completed.
1) Connect the output of the clock signal generator to
the input of the clock bandpass filter.
2) Connect the output of the clock bandpass filter to
the CLOCK SMA connector on the EV kit.
3) Connect the output of the analog signal generator
to the input of the analog bandpass filter.
_______________________________________________________________________________________
3
MAX19586/MAX19588 Evaluation Kits
Evaluate: MAX19586/MAX19588
Detailed Description
The MAX19586/MAX19588 EV kits are fully assembled
and tested PCBs that contain all the components nec-
essary to evaluate the performance of the MAX19586
or the MAX19588 ADCs. Digital data generated by the
ADCs is captured on a 16-bit bus (+ DOR bit). The EV
kits can be evaluated with a maximum clock frequency
(f
CLK
) of 80MHz for the MAX19586, or 100Msps for the
MAX19588.
The EV kits are designed as six-layer PCBs to optimize
the performance of the converter. The EV kits are
specified to have 3.3V and 1.8V power supplies
applied to the analog (AVDD) and digital (DVDD, VL)
power planes, respectively.
The digital outputs are available on connectors J5 or
J3 and J4. J5 is a 40-pin connector, which can directly
interface with a user-provided logic analyzer or data-
acquisition system. The digital output clock signal,
which is used to synchronize the output data to the
logic analyzer, is available at the CLKO pins on J5-3
and J1-1.
Reference Voltage
The full-scale range for the MAX19586/MAX19588 is
set to 2.56V
P-P
by an internal reference voltage. The
MAX19586/MAX19588’s internal reference voltage is
1.28V, and can be monitored at the REFOUT pad on
the EV kit. To use the internal reference voltage, the
reference input (REFIN) must be connected to the ref-
erence output (REFOUT) through resistor R12.
The MAX19586/MAX19588 EV kits also provide a
REFIN pad, allowing an external reference source to
be connected to the ADC. An external reference
source can be in the range of 1.28V ±10%.
Clock
A user-provided single-ended clock signal is convert-
ed to a differential clock signal through transformer T3.
To reduce clock jitter, the clock signal should have
high slew rates at its zero crossings. A large clock sig-
nal amplitude can be used to maximize the slew rate at
its zero crossings. Diode D1 limits the differential sig-
nal swing at the clock input when a large clock signal
is used to maximize the slew rate. The
MAX19586/MAX19588 EV kits are tested with a
+16dBm to +19dBm clock signal, with about 6dB loss
in the bandpass filter that follows the clock
signal generator.
Power Supplies
The MAX19586/MAX19588 EV kits require separate
analog and digital power supplies. A 3.3V power sup-
ply is used to power the analog portion of the ADC.
Two separate 1.8V power supplies are recommended:
DVDD powers the digital portion of the
MAX19586/MAX19588, and VL powers the buffer/
driver U2.
Analog Input Signal
The MAX19586/MAX19588 require a differential analog
input signal of less than or equal to +9.1dBm (2.56V
P-P
into 100Ω). The EV kits feature on-board transformer
3.3V
1.8V
1.8V
AV
DD
DV
DD
VL
HP/AGILENT 8644B
SYNC OUTPUT
CLOCK
BANDPASS FILTER
INPUT OUTPUT
MAX19586 EV KIT
OR MAX19588 EV KIT
J2
DOR
CLOCK
J5
16
LOGIC
ANALYZER
HP/AGILENT 8644B
SYNC OUTPUT
ANALOG
BANDPASS FILTER
INPUT OUTPUT
(OPTIONAL)
3dB
PAD
INPUT+
Figure 1. MAX19586/MAX19588 EV Kits Quick Start Setup and Connections
4
_______________________________________________________________________________________
MAX19586/MAX19588 Evaluation Kits
T1 that converts the output of a user-provided single-
ended signal to a differential signal for the ADC.
Transformer T1 has a primary-to-secondary turns ratio
of 1:1.414. Therefore, the single-ended signal should
have a power level of less than or equal to +9.1dBm
(1.81V
P-P
into 50Ω). Cable and bandpass filter losses
affect the amplitude of the received signal at the ADC.
Therefore, account for these losses when configuring
the signal input generator amplitude.
The EV kits accept a fully differential input signal after
making the following modifications:
• Cut the trace between resistor R1 PCB pads.
• Remove transformers T1 and T2.
• Install a 0.1µF (0603) ceramic capacitor on C2.
• Install 0Ω (0603) resistors on R2, R3, R4, and R5.
• Install an SMA connector on the INPUT- PCB
footprint.
applied to a latch that is capable of driving large
capacitive loads that may be present at the logic ana-
lyzer connection. The outputs of the buffer are con-
nected to two sets of connectors. The first set of con-
nectors includes J1 for the digital output clock signal,
J2 for the DOR bit, J3 and J4 for the digital output sig-
nals. This set of connectors accommodates the data-
acquisition and logic-analyzer systems such as
Tektronix’s TLA621. The second set of connectors con-
sists of a single 40-pin header, J5, which provides all
signals, except for the DOR bit, for logic-analyzer sys-
tems such as HP/Agilent 16500C. See Table 1 for
headers J1–J5 bit locations.
Note that a poor-quality connection may lead to
apparent performance degradation. To optimize
dynamic performance, avoid using “flying” (or indi-
vidual) lead logic-analyzer probes for collecting data
from the MAX19586/MAX19588 EV kits.
Evaluate: MAX19586/MAX19588
Digital Output Signals
The MAX19586/MAX19588 feature a 16-bit, parallel,
CMOS-compatible digital output bus and a DOR bit.
The digital outputs of the ADC and the DOR bit are
Table 1. Digital Output Bit Locations
BIT
CLKO
DOR
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
HEADERS
J1–J4
J1-1
J2-1
J3-1
J3-3
J3-5
J3-7
J3-9
J3-11
J3-13
J3-15
J4-1
J4-3
J4-5
J4-7
J4-9
J4-11
J4-13
J4-15
HEADER
J5
J5-3
—
J5-7
J5-9
J5-11
J5-13
J5-15
J5-17
J5-19
J5-21
J5-23
J5-25
J5-27
J5-29
J5-31
J5-33
J5-35
J5-37
Note:
All even numbered pins are connected to ground.
_______________________________________________________________________________________
5
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