Application Note 1029
Author: Chun Cheung, Ross O. Staffhorst
ISL6558EVAL1Z - Multi-Phase Power Conversion
For Routers and PC Peripherals Up To 100A
Abstract
This application note highlights design considerations for
a 150W power supply using Intersil’s ISL6558 4-Phase
Controller and ISL6612A Synchronous-Rectified Driver. A
step-by-step design procedure for a 12V-to-1.5V@100A
with 83% efficiency converter based on these two chips
is described; all formulae are applicable for a multi-phase
interleaved DC-DC buck converter. Thereafter,
experimental results with discussion give users a deeper
understanding of the performance of the reference
design and the advantages of the ISL6558 and
ISL6612A. Some operation and modification tips of the
evaluation board are included.
This application note first gives a brief introduction of
Intersil’s four-phase controller ISL6558 and
synchronous-rectified driver ISL6612A. A step-by-step
design procedure for a 12V-to-1.5V@100A, 500kHz, and
83% efficiency converter using the interleaved approach
follows. It includes all the fundamental formulae to
design a multi-phase interleaved DC-DC buck converter.
Thereafter, experimental results with discussion give
users a deeper understanding of the performance of the
reference design and the advantages of both ICs. Term
Definition, Reference, Schematics, and Layout are
included at the end of this application note.
Introduction
The changing computer performance landscape has
brought about the need for flexible power solutions.
Peripheral performance continues to increase as higher
speed bus interfaces are made available. Router designs
continue to grow in complexity as on-board processors
must perform more functions while continuing to
increase the speed of data transfer. This translates to
higher demands on the DC-DC converters which supply
them.
Intersil’s Endura
™
multi-phase controllers (HIP63xx and
ISL65xx) and synchronous-rectified buck MOSFET
drivers (ISL66xx) are suitable for the multi-channel
interleaved DC-DC buck converter implementation, as
shown in Figure 1, and provide superior performance
solutions to meet the above market demands.
Q1
Lo
Q2
Q1
Vin
Lin
Q2
Cin
Lo
Vo
Co
Intersil’s ISL6558 and
ISL6612A
The ISL6558 controller coupled with some ISL6612A
single-channel driver ICs form the basic building blocks
for applications which demand high current and rapid
load transient speed.
The ISL6558 regulates the output voltage and balances
load currents for two to four synchronous-rectified buck
converter channels; its internal structure is shown in
Figure 2. The internal 0.8V reference allows output
voltage selection down to that level with a 1% system
accuracy over-temperature. The current-channel balance
loop provides a better thermal balance among all phases.
Output voltage droop, or active voltage positioning, is
optional. Overvoltage and overcurrent monitors and
protection functions of the IC provide a safe environment
for microprocessor or other load. The controller is
available in a 16 Lead SOIC package and a space
economical 5mmx5mm
2
20 Lead QFN package. For more
detailed descriptions of the ISL6558 functionality, refer to
the device datasheet [1]
The ISL6612A is a driver IC capable of delivering up to
2A of gate-charge current for rapidly switching both
MOSFETs in a synchronous-rectified bridge. The
ISL6612A accepts a single logic input to control both
upper and lower MOSFETs. Its Tri-State® feature,
working together with Intersil’s Multi-Phase PWM
controllers, helps prevent a negative transient on the
output voltage when the output is being shut down. This
eliminates the Schottky diode that is used in some
systems for protecting the microprocessor from
reversed-output-voltage damage. Furthermore, adaptive
shoot-through protection is provided on both switching
edges to provide optimal dead time and minimize
conduction losses. Bootstrap circuitry permits greater
enhancement of the upper MOSFET. For a more detailed
description of the ISL6612A, refer to the device data
sheet [2]. In addition, the ISL6614A/ISL6610
dual-channel driver IC provides equivalent functionality
with some space savings [3].
Q1
Lo
Q2
FIGURE 1. MULTI-PHASE INTERLEAVED BUCK
CONVERTER
July 31, 2009
AN1029.3
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774
|
Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2002, 2009. All Rights Reserved
Endura™ is a trademark of Intersil Americas Inc. Tri-State® is a registered trademark of National Semiconductor Corp.
All other trademarks mentioned are the property of their respective owners.
Application Note 1029
PGOOD
VCC
VSEN
X 0.9
-
POWER-ON
RESET (POR)
OV
LATCH
S
R
CLOCK AND
SAWTOOTH
GENERATOR
TRI-STATE®
UV
+
FS/EN
+
PWM
-
X1.15
+
OV
-
+
∑
-
+
PWM1
SOFT-
START
AND FAULT
LOGIC
COMP
∑
-
+
PWM
-
PWM2
+
∑
-
0.8V
REFERENCE
+
E/A
-
+
+
PWM
-
PWM3
∑
-
+
PWM
-
PHASE
NUMBER
PWM4
FB
DROOP
I
TOTAL
+
+
+
CURRENT
CORRECTION
CHANNEL
DETECTOR
ISEN1
ISEN2
ISEN3
ISEN4
∑
+
+
OC
- I
TRIP
GND
FIGURE 2. ISL6558 INTERNAL STRUCTURE
2
AN1029.3
July 31, 2009
Application Note 1029
CH1 PWM
CH2 PWM
CH3 PWM
CH4 PWM
D
1-D
1-D
D
D
D
I
Lo,PP
I
LO,1
/L
O
Io
----
-
N
V
O
/L
O
)
O
I
LO,3
Io
-----
N
I
LO,4
-
(m
D
N
X
L
O
)/
(V
I
LO,2
IN
-
V
Io
----
-
N
Io
-----
N
I
PP
/L
O
I
PP
V
IN
0
I
Q2
IN
-
I
Q2
CH1, UPPER AND
LOWER FETS
CURRENT
I
Q1
I
Lo,PP
CH2, UPPER AND
LOWER FETS
CURRENT
I
Q2
V
O
/L
V
O
)
I
Q1
Io
----
-
N
O
(V
I
Q1
Io
----
-
N
I
Q2
CH3, UPPER AND
LOWER FETS
CURRENT
CH4, UPPER AND
LOWER FETS
CURRENT
I
Q1
Io
----
-
N
I
Q2
I
Q1
Io
----
-
N
FIGURE 3. FOUR-CHANNEL INTERLEAVED DC-DC BUCK CONVERTER TIMING DIAGRAM
Converter Design
This section summarizes a step-by-step procedure for a
12V-to-1.5V@100A power supply for high current and
high transient speed applications. The terms used in all
equations are defined at the end of this application note,
unless otherwise stated in the text. Some fundamental
formulae to calculate RMS values of triangular and
trapezoid waveforms and to derive most equations in this
application note are defined in the following.
CASE 1
Δ
I
Ib
Ia
D
Ic
1
–
D
Irms1
=
Δ
I
2
-
Ic
2
+ -------
12
Ib
CASE 2
0
⎛
Ic
2
+
Δ
I
-
⎞ •
D
-------
⎝
12
⎠
2
Δ
I
Ic
D
Ia
Irms2
=
3
AN1029.3
July 31, 2009
Application Note 1029
Δ
I
CASE 3
0
Ib
Ia
1
–
D
2
⎛
Ic
2
+
Δ
I
-
⎞ • (
1
–
D
)
-------
⎝
12
⎠
Ic
a rough idea of the range of optimum frequencies and
efficiencies for a particular application. Note that the
higher the switching frequency, the higher the loop
bandwidth (typically 1/10 to 1/3 of the switching
frequency) potentially achieved, resulting in fewer output
capacitors to meet the same transient performance.
Equation 1 defines the duty cycle of each channel, and it
should be no greater than 75% (maximum duty cycle of
the ISL6558) at the minimum operational input line and
the maximum fully loaded output. The drops due to the
PCB resistances are included in the equation, and they
are very significant portions especially for high current
applications.
Io
-
Vo
+
(
R
Q2
+
R
Lo
+
R
Bo
) •
----
N
-
D
= ----------------------------------------------------------------------------
Io
-
V
2
+
(
R
Q2
–
R
Q1
) •
----
N
where
(EQ. 1)
Irms3
=
Ib
CASE 4
Ia
D
Δ
I
2
-
Ic
2
• (
D
–
D
2
)
+ -------
•
D
12
Ia
+
Ib
-
Ic
= ----------------
2
Id
=
Ic
•
D
Δ
I
=
Ib
–
Ia
Δ
I
0
–
Id
Irms4
=
where
Io
-
V
2
=
V
IN
–
(
R
Lin
+
R
Bin
) •
I
IN
–
⎛
---- –
I
IN
⎞ •
ESR
IN
⎝
N
⎠
Io
-
Vo
=
Vo
NL
–
V
DROOP
•
---------------
Io
Vo
•
Io
-
I
IN
= ------------------
η •
V
IN
DETERMINE NUMBER OF PHASES, SWITCHING
FREQUENCY, AND DUTY CYCLE
The first step in designing a multi-phase converter is to
determine the number of phases. This determination
depends heavily on the cost analysis, which in turn
depends on system constraints that differ from one
design to the next. Principally, the designer will be
concerned with whether components can be mounted on
both sides of the circuit board; whether through-hole
components are permitted on either side; and the total
board space available for power-supply circuitry.
Generally speaking, the most economical solution will be
for each phase to handle between 15A and 20A. All
surface mount designs will tend toward the lower end of
this current range; if through-hole MOSFETs can be used,
higher per-phase currents are possible. In cases where
board space is the limiting constraint, current can be
pushed as high as 30A per phase, but these designs
typically require heat sinks and forced air to cool the
MOSFETs. Paralleling MOSFETs in each leg is another way
to push per-phase currents even higher, but the power
and thermal stresses on each driver should be evaluated
carefully. In such a case, a 5V driver such as Intersil’s
ISL6609 could be considered. See “DRIVER LOSSES
CALCULATION” on page 8. In the reference design, all
four phases of the ISL6558 are used to deliver 100A of
total output current.
There are a number of variables to consider when
choosing the switching frequency for a particular
application. The size of the converter, the overall losses
of magnetics components, the switching losses of power
MOSFETs, the desired efficiency, the transient response,
and the maximum achievable duty cycle should all be
under consideration. It requires an iterative process,
monitoring changes of the above parameters, to obtain
an optimum switching frequency for a particular
application. Equations presented in this paper can be
used to develop a MathCAD worksheet that helps obtain
4
max
In Equation 1, Vo
NL
is the output voltage at no load, V
IN
is the input voltage, N is the number of active channels,
I
IN
and Io are the input and output currents,
respectively. R
Q1
and R
Q2
are the r
DS(ON)
’s of upper and
lower FETs, respectively. R
Lin
and R
Lo
are the equivalent
resistances of input and output inductors, respectively.
R
Bin
and R
Bo
are the input and output PCB resistances
(including the connectors resistances), respectively.
OUTPUT FILTER DESIGN
The switching of each channel in a multi-phase converter
is timed to be symmetrically out of phase with each of
the other channels. In an N-phase converter, each
channel switches 1/N cycle after the previous channel
and 1/N cycle before the following channel. As a result,
the N-phase converter has a combined ripple frequency
N times the ripple frequency of any one phase. In
addition, the peak-to-peak amplitude of the combined
inductor currents is reduced in proportion to the number
of active phases. Increased ripple frequency and lower
current ripple amplitude mean that the designer can use
less per-channel inductance and lower total output
capacitance for any performance specification. Note that
the higher the inductor ripple current, the higher the
switching and conduction losses of each-channel’s bridge
MOSFETs. See “Lower MOSFET Power Calculation” on
page 7 and “Upper MOSFET Power Calculation” on
page 8.
AN1029.3
July 31, 2009
Application Note 1029
Equation 2 represents an individual channel’s
peak-to-peak inductor current. Equation 3 represents the
combined ripple current filtered by the output capacitors.
V
1
• (
1
–
D
)
I
Lo
,
PP
= ------------------------------
-
L o
•
Fsw
where
Io
-
V
1
=
Vo
+ ----
• (
R
Q1
+
R
Lo
+
R
Bo
)
N
(EQ. 3)
(EQ. 2)
2
I
Lo
,
PP
⎛
Io
⎞
2
+ -----------------
-
----
-
⎝
N
⎠
12
I
Lo
,
RMS
=
(EQ. 6)
I
I
Lo
,
PEAK
=
Io
+ -----------------
-
----
Lo
,
PP
-
2
N
V
1
(
N
•
D
–
m
+
1
) • (
m
–
N
•
D
)
-
-
Lo
= --------------------------
⎛
---------------------------------------------------------------------------
⎞
⎠
I
PP
•
Fsw
⎝
N
•
D
(EQ. 7)
(EQ. 8)
V
1
(
N
•
D
–
m
+
1
) • (
m
–
N
•
D
)
-
I
PP
= ------------------------
⎛
---------------------------------------------------------------------------
⎞
⎠
Lo
•
Fsw
⎝
N
•
D
for
m
–
1
≤
N
•
D
≤
m
m
=
ROUNDUP
(
N
•
D
,
0
)
The output capacitors conduct the ripple component of
the inductor current. In the case of multi-phase
converters, the capacitor current is the sum of the ripple
currents from each individual channel, as defined in
Equation 3, and its RMS value is defined in Equation 9.
Io
RMS
=
2
I
PP
--------
-
12
(EQ. 9)
RIPPLE CURRENT MULTIPLIER, K
CM
1
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
4
3
dV
ESR
0
2
N=1
Besides being able to handle the heat that is generated
by their equivalent series resistance (ESR), the output
capacitors should be designed to meet the output voltage
ripple and load transient requirements. For high dI/dt
loads, the output voltage ripple will be within the limits
when the requirements for the load transient are met.
+
-
0.9
1
0
dV
ESL
+
-
dV ESR
=
I PP
•
E
(
d
S
)R
DUTY CYCLE (V
O
/V
IN
)
FIGURE 4. RIPPLE CURRENT MUTIPLIER VS. DUTY
In Equation 3, m is the nearest integer that is rounded
up from the product of the number of active channels
and the individual channel duty cycle, and it represents
the maximum number of channels having positive slopes
within any time interval. In the reference design, m is
one. If the total ripple current (I
PP
) is normalized to the
parameter K
NORM
, i.e, I
Lo,PP
at zero duty cycle, then the
ripple current multiplier (K
CM
) can be defined as in
Equation 5, which is a function of channel duty cycle,
number of active channels, and m.
V
1
K
NORM
= ------------------------
Lo
•
Fsw
(
N
•
D
–
m
+
1
) • (
m
–
N
•
D
)
-
K
CM
= ---------------------------------------------------------------------------
N
•
D
(EQ. 4)
(EQ. 5)
ESL
-
dV ESL
= -----------
•
V IN
L
dV
Co
0
-
-
dV
I PP
1
-
= -------
•
-------------------------------
Co
Co 8
•
N
•
Fsw
FIGURE 5. OUTPUT VOLTAGE RIPPLE COMPONENTS
In addition to Equation 3, the total output ripple current
can be determined by the product of the ripple current
multiplier (K
CM
) read from Figure 4 and the
normalization factor, K
NORM
.
The RMS and peak currents through the single-channel
inductor are defined in Equations 6 and 7, respectively.
As a rule of thumb, the total output ripple current should
set around 10% to 20% of full load; the required channel
inductor value then can be derived from Equation 3,
rearranged in Equation 8.
The output voltage ripple can be conservatively
approximated by Equation 10. The first two terms
(dV
ESR
and dV
ESL
) contributed by the equivalent series
resistance (ESR) and the equivalent series inductance
(ESL) of the output capacitors are the dominant ones and
are normally accurate enough to estimate the ripple
voltage. The last term (dV
Co
) contributed by the output
capacitance (Co) is normally much smaller and can be
neglected since the peak of the dV
Co
happens at the
ripple current zero crossing and does not align with the
peak of dV
ESR
, as shown in Figure 5.
I
PP
ESL
1
-
-
-
Vo
RIPPLE
≈
I
PP
•
ESR
+ -----------
•
V
IN
+ -------
•
------------------------------
(EQ. 10)
Lo
Co 8
•
N
•
Fsw
5
AN1029.3
July 31, 2009
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