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Nexys4 DDR™ FPGA Board Reference Manual
Nexys4 DDR rev. C; Revised April 11, 2016
1
Overview
The Nexys4 DDR board is a complete, ready-to-use digital circuit
development platform based on the latest Artix-7™ Field
Programmable Gate Array (FPGA) from Xilinx®. With its large,
high-capacity FPGA (Xilinx part number XC7A100T-1CSG324C),
generous external memories, and collection of USB, Ethernet, and
other ports, the Nexys4 DDR can host designs ranging from
introductory combinational circuits to powerful embedded
processors. Several built-in peripherals, including an
accelerometer, temperature sensor, MEMs digital microphone, a
speaker amplifier, and several I/O devices allow the Nexys4 DDR
to be used for a wide range of designs without needing any other
components.
The Nexys4 DDR
The Artix-7 FPGA is optimized for high performance logic, and offers more capacity, higher performance, and more
resources than earlier designs. Artix-7 100T features include:
15,850 logic slices, each with four 6-input LUTs and 8 flip-flops
4,860 Kbits of fast block RAM
Six clock management tiles, each with phase-locked loop (PLL)
240 DSP slices
Internal clock speeds exceeding 450 MHz
On-chip analog-to-digital converter (XADC)
The Nexys4 DDR also offers an improved collection of ports and peripherals, including:
16 user switches
USB-UART Bridge
12-bit VGA output
3-axis accelerometer
128MiB DDR2
Pmod for XADC signals
16 user LEDs
Two tri-color LEDs
PWM audio output
Temperature sensor
Serial Flash
Digilent USB-JTAG port for FPGA
programming and
communication
Two 4-digit 7-segment displays
Micro SD card connector
PDM microphone
10/100 Ethernet PHY
Four Pmod ports
USB HID Host for mice, keyboards
and memory sticks
The Nexys4 DDR is compatible with Xilinx’s new high-performance Vivado® Design Suite as well as the ISE® toolset,
which includes ChipScope™ and EDK. Xilinx offers free WebPACK™ versions of these toolsets, so designs can be
implemented at no additional cost. The Nexys4 DDR is not supported by the Digilent Adept Utility.
DOC#: 502-292
Copyright Digilent, Inc. All rights reserved.
Other product and company names mentioned may be trademarks of their respective owners.
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Nexys4 DDR™ FPGA Board Reference Manual
Figure 1. Nexys4 DDR board features.
Callout
1
2
3
4
5
6
7
8
9
10
11
12
Component Description
Power select jumper and battery header
Shared UART/ JTAG USB port
External configuration jumper (SD / USB)
Pmod port(s)
Microphone
Power supply test point(s)
LEDs (16)
Slide switches
Eight digit 7-seg display
JTAG port for (optional) external cable
Five pushbuttons
Temperature sensor
Callout
13
14
15
16
17
18
19
20
21
22
23
24
Component Description
FPGA configuration reset button
CPU reset button (for soft cores)
Analog signal Pmod port (XADC)
Programming mode jumper
Audio connector
VGA connector
FPGA programming done LED
Ethernet connector
USB host connector
PIC24 programming port (factory use)
Power switch
Power jack
A growing collection of board support IP, reference designs, and add-on boards are available on the Digilent
website. See the Nexys4 DDR page at
www.digilentinc.com
for more information.
Copyright Digilent, Inc. All rights reserved.
Other product and company names mentioned may be trademarks of their respective owners.
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Nexys4 DDR™ FPGA Board Reference Manual
1.1
Migrating from Nexys4
The Nexys4 DDR is an incremental update to the Nexys4 board. The major improvement is the replacement of the
16 MiB CellularRAM with a 128 MiB DDR2 SDRAM memory. Digilent will provide a VHDL reference module that
wraps the complexity of a DDR2 controller and is backwards compatible with the asynchronous SRAM interface of
the CellularRAM, with certain limitations. See the Nexys4 DDR page at
www.digilentinc.com
for updates.
Furthermore, to accommodate the new memory, the pin-out of the FPGA banks has changed as well. The
constraints file of existing projects will need to be updated.
The audio output (AUD_PWM) needs to be driven open-drain as opposed to push-pull on the Nexys4.
2
Power Supplies
The Nexys4 DDR board can receive power from the Digilent USB-JTAG port (J6) or from an external power supply.
Jumper JP3 (near the power jack) determines which source is used.
All Nexys4 DDR power supplies can be turned on and off by a single logic-level power switch (SW16). A power-good
LED (LD22), driven by the “power good” output of the ADP2118 supply, indicates that the supplies are turned on
and operating normally. An overview of the Nexys4 DDR power circuit is shown in Figure 2.
Power
Jack
(J13)
Power
Switch
(SW16)
VU5V0
VIN
EN
VIN
3A
PGOOD
150mA
Audio
3.3V
3.3V
Power On
LED (LD22)
JP3
Micro-USB
Port (J6)
J12
R287
EN
D16
IC17: ADP2118
VIN
Power Source Select
JP3
J12
USB
WALL
BATTERY
EN
800 mA
1.8V
IC23: ADP2138
VIN
EN
PGOOD
3A
1.0V
IC22: ADP2118
Figure 2. Nexys4 DDR power circuit.
The USB port can deliver enough power for the vast majority of designs. Our out-of-box demo draws ~400mA of
current from the 5V input rail. A few demanding applications, including any that drive multiple peripheral boards,
might require more power than the USB port can provide. Also, some applications may need to run without being
connected to a PC’s USB port. In these instances, an external power supply or battery pack can be used.
An external power supply can be used by plugging into to the power jack (JP3) and setting jumper J13 to “wall”.
The supply must use a coax, center-positive 2.1mm internal-diameter plug, and deliver 4.5VDC to 5.5VDC and at
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Nexys4 DDR™ FPGA Board Reference Manual
least 1A of current (i.e., at least 5W of power). Many suitable supplies can be purchased from Digilent, through
Digi-Key, or other catalog vendors.
An external battery pack can be used by connecting the battery’s positive terminal to the center pin of JP3 and the
negative terminal to the pin labeled J12, directly below JP3. Since the main regulator on the Nexys4 DDR cannot
accommodate input voltages over 5.5VDC, an external battery pack must be limited to 5.5VDC. The minimum
voltage of the battery pack depends on the application: if the USB Host function (J5) is used, at least 4.6V needs to
be provided. In other cases, the minimum voltage is 3.6V.
Voltage regulator circuits from Analog Devices create the required 3.3V, 1.8V, and 1.0V supplies from the main
power input. Table 1 provides additional information. Typical currents depend strongly on FPGA configuration and
the values provided are typical of medium size/speed designs.
Supply
3.3V
1.0V
1.8V
Circuits
FPGA I/O, USB ports, Clocks,
RAM I/O, Ethernet, SD slot,
Sensors, Flash
FPGA Core
DDR2, FPGA Auxiliary and
RAM
Device
IC17: ADP2118
IC22: ADP2118
IC23: ADP2138
Current (max/typical)
3A/0.1 to 1.5A
3A/ 0.2 to 1.3A
0.8A/ 0.5A
Table 1. Nexys4 DDR power supplies.
2.1
Power protection
The Nexys4 DDR features overcurrent and overvoltage protection on the input power rail. A 3.5A fuse (R287) and a
5V Zener diode (D16) provide a non-resettable protection for other on-board integrated circuits, as displayed in
Figure 2. Applying power outside of the specs outlined in this document is not covered by warranty. If this
happens, either or both might get permanently damaged. The damaged parts are not user-replaceable.
3
FPGA Configuration
After power-on, the Artix-7 FPGA must be configured (or programmed) before it can perform any functions. You
can configure the FPGA in one of four ways:
1.
2.
3.
4.
A PC can use the Digilent USB-JTAG circuitry (portJ6, labeled “PROG”) to program the FPGA any time the
power is on.
A file stored in the nonvolatile serial (SPI) flash device can be transferred to the FPGA using the SPI port.
A programming file can be transferred to the FPGA from a micro SD card.
A programming file can be transferred from a USB memory stick attached to the USB HID port.
Copyright Digilent, Inc. All rights reserved.
Other product and company names mentioned may be trademarks of their respective owners.
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Nexys4 DDR™ FPGA Board Reference Manual
USB-JTAG/UART Port
Micro-AB USB
Connector (J6)
USB
Controller
JTAG
Port
SPI
Port
SPI Quad mode
Flash
6-pin JTAG
Header (J10)
1x6 JTAG
Header
Mode (JP1)
Artix-7
M0
M2
M1
JP2
NA
JP1
SPI Flash
JTAG
USB
MicroSD
Micro SD
Connector (J1)
Type A USB Host
Connector (J5)
User I/O
NA
2
PIC24
Serial
Prog. Port
Done
Prog
Programming Mode
Media Select
(JP2)
Figure 3. Nexys4 DDR configuration options.
Figure 3 shows the different options available for configuring the FPGA. An on-board “mode” jumper (JP1) and a
media selection jumper (JP2) select between the programming modes.
The FPGA configuration data is stored in files called bitstreams that have the .bit file extension. The ISE or Vivado
software from Xilinx can create bitstreams from VHDL, Verilog®, or schematic-based source files (in the ISE toolset,
EDK is used for MicroBlaze™ embedded processor-based designs).
Bitstreams are stored in SRAM-based memory cells within the FPGA. This data defines the FPGA’s logic functions
and circuit connections, and it remains valid until it is erased by removing board power, by pressing the reset
button attached to the PROG input, or by writing a new configuration file using the JTAG port.
An Artix-7 100T bitstream is typically 30,606,304 bits and can take a long time to transfer. The time it takes to
program the Nexys4 can be decreased by compressing the bitstream before programming, and then allowing the
FPGA to decompress the bitstream itself during configuration. Depending on design complexity, compression
ratios of 10x can be achieved. Bitstream compression can be enabled within the Xilinx tools (ISE or Vivado) to occur
during generation. For instructions on how to do this, consult the Xilinx documentation for the toolset being used.
After being successfully programmed, the FPGA will cause the "DONE" LED to illuminate. Pressing the “PROG”
button at any time will reset the configuration memory in the FPGA. After being reset, the FPGA will immediately
attempt to reprogram itself from whatever method has been selected by the programming mode jumpers.
The following sections provide greater detail about programming the Nexys4 DDR using the different methods
available.
3.1
JTAG Configuration
The Xilinx tools typically communicate with FPGAs using the Test Access Port and Boundary-Scan Architecture,
commonly referred to as JTAG. During JTAG programming, a .bit file is transferred from the PC to the FPGA using
the onboard Digilent USB-JTAG circuitry (port J6) or an external JTAG programmer, such as the Digilent JTAG-HS2,
attached to port J10. You can perform JTAG programming any time after the Nexys4 DDR has been powered on,
regardless of what the mode jumper (JP1) is set to. If the FPGA is already configured, then the existing
configuration is overwritten with the bitstream being transmitted over JTAG. Setting the mode jumper to the JTAG
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