USER’S MANUAL
ISL8117EVAL2Z
Evaluation Board User Guide
UG020
Rev 0.00
March 17, 2015
Description
The ISL8117EVAL2Z evaluation board (shown in
Figure 1)
features the
ISL8117.
The ISL8117 is a 60V high voltage
synchronous buck controller that offers external soft-start,
independent enable functions and integrates UV/OV/OC/OT
protection. Its current mode control architecture and internal
compensation network keep peripheral component count
minimal. Programmable switching frequency ranging from
200kHz to 2MHz helps to optimize inductor size while the
strong gate driver delivers up to 30A for the buck output.
Key Features
• Wide input range: 18V to 60V
• High light-load efficiency in pulse skipping DEM operation
• Programmable soft-start
• Optional DEM/CCM operation
• Supports prebias output with SR soft-start
• External frequency sync
• PGOOD indicator
• OCP, OVP, OTP, UVP protection
• Back biased from output to improve efficiency
Specifications
The ISL8117EVAL2Z evaluation board is designed for high
current applications. The current rating of the ISL8117EVAL2Z
is limited by the FETs and inductor selected. The ISL8117 gate
driver is capable of delivering up to 20A for the buck output as
long as the proper FETs and inductor are provided. The
electrical ratings of ISL8117EVAL2Z are shown in
Table 1.
TABLE 1. ELECTRICAL RATING
PARAMETER
Input Voltage
18V to 60V
RATING
References
ISL8117
Datasheet
Ordering Information
PART NUMBER
ISL8117EVAL2Z
DESCRIPTION
High Voltage PWM Step-down
Synchronous Buck Controller Evaluation
Board
Switching Frequency 300kHz
Output Voltage
Output Current
OCP Set Point
12V
20A
Minimum 25A at ambient room temperature
FIGURE 1.
ISL8117EVAL2Z TOP SIDE
UG020 Rev 0.00
March 17, 2015
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ISL8117EVAL2Z
Recommended Testing
Equipment
The following materials are recommended to perform testing:
• 0V to 60V power supply with at least 30A source current
capability
• Electronic loads capable of sinking current up to 30A
• Digital Multimeters (DMMs)
• 100MHz quad-trace oscilloscope
Functional Description
The ISL8117EVAL2Z is the same test board used by the Intersil
application engineers and IC designers to evaluate the
performance of the ISL8117 QFN IC. The board is set to provide
an easy and complete evaluation of all the IC and board
functions.
As shown in
Figure 3 on page 3,
18V to 60V V
IN
is supplied to J1
(+) and J2 (-). The regulated 12V output on J3 (+) and J4 (-) can
supply up to 20A to the load. Due to the high thermal efficiency,
the evaluation board can run at 20A continuously without airflow
under room temperature ambient conditions.
Test points TP1 through TP19 provide easy access to IC pin and
external signal injection terminals.
As shown in
Table 2,
connector J5 provides selection of either
CCM mode (shorting pin 1 and pin 2) or DEM mode (shorting
pin 2 and pin 3). Connector J6 provides an option to disable the
converter by shorting its pin 1 and 2.
Quick Test Guide
1. Jumper J5 provides the option to select CCM or DEM. Please
refer to
Table 2
for the desired operating option. Ensure that
the circuit is correctly connected to the supply and electronic
loads prior to applying any power. Please refer to
Figure 3
for
proper set-up.
2. Turn on the power supply.
3. Adjust input voltage V
IN
within the specified range and
observe output voltage. The output voltage variation should
be within 3%.
4. Adjust load current within the specified range and observe
output voltage. The output voltage variation should be
within 3%.
5. Use an oscilloscope to observe output voltage ripple and
Phase node ringing. For accurate measurement, please refer
to
Figure 2
for proper test set-up.
TABLE 2. DESIRED OPERATING OPTIONS
JUMPER
#
J5
POSITION
CCM (Pin 1-2)
DEM (Pin 2-3)
J6
(Pin 1-2)
FUNCTION
Continuous current mode
Diode emulation mode
Disable the PWM
Operating Range
The input voltage range is from 18V to 60V for an output voltage
of 12V. If the output voltage is set to a lower value, the minimum
V
IN
can be reset to a lower value by changing the ratio of R
4
and
R
5
. The minimum EN threshold that V
IN
can be set to is 4.5V.
The rated load current is 20A with the OCP point set at minimum
25A at room ambient condition.
The operating temperature range is from -40°C to +125°C.
Please note that airflow is needed for higher temperature
ambient conditions.
PCB Layout Guideline
Careful attention to layout requirements is necessary for
successful implementation of an ISL8117 based DC/DC
converter. The ISL8117 switches at a very high frequency and
therefore the switching times are very short. At these switching
frequencies, even the shortest trace has significant impedance.
Also, the peak gate drive current rises significantly in an
extremely short time. Transition speed of the current from one
device to another causes voltage spikes across the
interconnecting impedances and parasitic circuit elements.
These voltage spikes can degrade efficiency, generate EMI, and
increase device overvoltage stress and ringing. Careful
component selection and proper PC board layout minimizes the
magnitude of these voltage spikes.
There are three sets of critical components in a DC/DC converter
using the ISL8117: the controller, the switching power
components and the small signal components. The switching
power components are the most critical from a layout point of
view because they switch a large amount of energy, which tends
to generate a large amount of noise. The critical small signal
components are those connected to sensitive nodes or those
supplying critical bias currents. A multilayer printed circuit board
is recommended.
OUTPUT CAP
OR MOSFET
FIGURE 2. PROPER PROBE SET-UP TO MEASURE OUTPUT RIPPLE
AND PHASE NODE RINGING
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March 17, 2015
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ISL8117EVAL2Z
Layout Considerations
1. The input capacitors, upper FET, lower FET, inductor and
output capacitor should be placed first. Isolate these power
components on the top side of the board with their ground
terminals adjacent to one another. Place the input high
frequency decoupling ceramic capacitors very close to the
MOSFETs.
2. Use separate ground planes for power ground and small
signal ground. Connect the SGND and PGND together close to
the IC. DO NOT connect them together anywhere else.
3. The loop formed by the input capacitor, the top FET and the
bottom FET must be kept as small as possible.
4. Ensure the current paths from the input capacitor to the
MOSFET, to the output inductor and the output capacitor are
as short as possible with maximum allowable trace widths.
5. Place the PWM controller IC close to the lower FET. The LGATE
connection should be short and wide. The IC can be best
placed over a quiet ground area. Avoid switching ground loop
currents in this area.
6. Place VCC5V bypass capacitor very close to the VCC5V pin of
the IC and connect its ground to the PGND plane.
7. Place the gate drive components (optional BOOT diode and
BOOT capacitors) together near the controller IC.
8. The output capacitors should be placed as close to the load as
possible. Use short wide copper regions to connect output
capacitors to load in order to avoid inductance and
resistances.
9. Use copper filled polygons or wide but short trace to connect
the junction of the upper FET, lower FET and output inductor.
Also keep the PHASE node connection to the IC short. DO NOT
unnecessarily oversize the copper islands for the PHASE
node. Since the phase nodes are subjected to very high dv/dt
voltages, the stray capacitor formed between these islands
and the surrounding circuitry will tend to couple switching
noise.
10. Route all high speed switching nodes away from the control
circuitry.
11. Create a separate small analog ground plane near the IC.
Connect the SGND pin to this plane. All small signal grounding
paths including feedback resistors, current limit setting
resistor, soft-starting capacitor and EN pull-down resistors
should be connected to this SGND plane.
12. Separate the current sensing trace from the PHASE node
connection.
13. Ensure the feedback connection to the output capacitor is
short and direct.
A
LOAD
+
-
A
-
+
-
+
V
IN
V
FIGURE 3. PROPER TEST SET-UP
.
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March 17, 2015
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ISL8117EVAL2Z
Typical Evaluation Board Performance Curves
100
95
90
EFFICIENCY (%)
85
80
75
70
65
60
0
2
4
6
8
10
12
I
OUT
(A)
14
16
18
20
EFFICIENCY (%)
V
IN
= 48V
V
IN
= 60V
V
IN
= 36V
V
IN
= 24V
V
IN
= 18V
100
95
90
85
80
75
70
65
60
0
2
4
V
IN
= 48V, unless otherwise noted.
V
IN
= 48V
V
IN
= 60V
V
IN
= 36V
V
IN
= 24V
V
IN
= 18V
6
8
10
12
I
OUT
(A)
14
16
18
20
FIGURE 4. CCM EFFICIENCY vs LOAD
FIGURE 5. DEM EFFICIENCY vs LOAD
12.20
12.18
12.16
12.14
V
OUT
(V)
12.12
12.10
12.08
12.06
12.04
12.02
12.00
0
2
4
6
V
IN
= 60V
V
IN
= 36V
8
10
I
OUT
(A)
V
IN
= 24V
12
14
16
18
20
V
IN
= 48V
V
OUT
(V)
V
IN
= 18V
12.20
12.18
12.16
12.14
12.12
12.10
12.08
12.06
12.04
12.02
I
O
= 20A
I
O
= 10A
I
O
= 0A
12.00
18
23
28
33
38
V
IN
(V)
43
48
53
58
FIGURE 6.
CCM MODE LOAD REGULATION
FIGURE 7. CCM MODE LINE REGULATION
5
PHASE 50V/DIV
CCM
0.5
I
IN
(A)
LGATE 5V/DIV
CLKOUT 5V/DIV
0.05
DEM
0.005
0.01
0.1
I
OUT
(A)
1
10
1µs/DIV
I
L
5A/DIV
FIGURE 8. INPUT CURRENT COMPARISON WITH MODE = CCM/DEM
FIGURE 9. PHASE, LGATE, CLKOUT AND INDUCTOR CURRENT
WAVEFORMS
UG020 Rev 0.00
March 17, 2015
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ISL8117EVAL2Z
Typical Evaluation Board Performance Curves
V
IN
= 48V, unless otherwise noted. (Continued)
NO LOAD, V
IN
= 48V
NO LOAD, V
IN
= 48V
V
OUT
50mV/DIV
1ms/DIV
20A LOAD, V
IN
= 48V
20A LOAD, V
IN
= 48V
V
OUT
50mV/DIV
V
OUT
50mV/DIV
V
OUT
50mV/DIV
4µs/DIV
4µs/DIV
FIGURE 10. OUTPUT RIPPLE, MODE = CCM
FIGURE 11. OUTPUT RIPPLE, MODE = DEM
V
OUT
5V/DIV
V
OUT
5V/DIV
BURST MODE OPERATION
BOOT CAP REFRESH
EXTBIAS KICK-IN
LGATE 5V/DIV
BOOT CAP REFRESH
EXTBIAS KICK-IN
LGATE 5V/DIV
CLKOUT 5V/DIV
CLKOUT 5V/DIV
DEM TO CCM TRANSITION
4ms/DIV
I
L
10A/DIV
4ms/DIV
I
L
5A/DIV
FIGURE 12. START-UP WAVEFORMS; MODE = CCM, LOAD = 0A,
V
IN
= 48V
FIGURE 13. START-UP WAVEFORMS; MODE = DEM, LOAD = 0A,
V
IN
= 48V
V
OUT
5V/DIV
SS 1V/DIV
V
OUT
5V/DIV
SS 1V/DIV
EN 5V/DIV
PGOOD 5V/DIV
EN 5V/DIV
PGOOD 5V/DIV
20ms/DIV
20ms/DIV
FIGURE 14. START-UP WAVEFORMS; MODE = CCM, LOAD = 0A,
V
IN
= 48V
FIGURE 15. START-UP WAVEFORMS; MODE = DEM, LOAD = 0A,
V
IN
= 48V
UG020 Rev 0.00
March 17, 2015
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