19-4474; Rev 0; 2/09
EVALUATION KIT AVAILABLE
MAX3673 Evaluation Kit
General Description
The MAX3673 evaluation kit (EV kit) is a fully assembled
and tested demonstration board that simplifies evalua-
tion of the MAX3673 low-jitter frequency synthesizer
with selectable input reference. The EV kit includes
slide switches to allow easy selection of different
modes of operation. Clock I/Os have SMA connectors
and are AC-coupled to simplify connection to test
equipment. The EV kit is powered by a +3.3V supply
and uses LEDs for signal status indicators.
♦
Fully Assembled and Tested
♦
Slide Switches for Mode Control
♦
SMA Connectors and AC-Coupled Clock I/Os
♦
Powered by +3.3V Supply
♦
LED Signal Status Indicators
Features
Evaluates: MAX3673
Ordering Information
PART
MAX3673EVKIT+
TYPE
EV Kit
+Denotes
lead(Pb)-free and RoHS compliant.
Component List
DESIGNATION QTY
C1, C6, C7
C11–C13, C16,
C18–C22,
C24–C27, C29,
C30, C32–C39,
C41, C42,
C46–C50,
C62, C63
C2
C3
C4
C5
C28
D1, D3, D8
D2, D4, D7
J1, J2,
J5–J12, J14,
J15, J19, J20,
J22–J29,
J44, J45
J4, J13
L1
DESCRIPTION
DESIGNATION QTY
R1–R5, R15,
R16, R17,
R37–R46
R6–R11
R12, R13, R14,
R18, R21, R22
R23, R24, R25
1
1
1
1
1
3
3
33μF
±5%
tantalum capacitor
(B case)
2.2μF
±10%
ceramic capacitor (0805)
0.1μF
±10%
ceramic capacitor (0603)
0.01μF
±10%
ceramic capacitor
(0603)
0.22μF
±10%
ceramic capacitor
(0402)
Green SMD LEDs (1206)
Panasonic LNJ311G8PRA
Red SMD LEDs (1206)
Panasonic LNJ211R8ARA
SMA connectors, edge-mount,
tab center
Johnson 142-0701-851
Test points
Keystone 5000
4.7μH
±20%
inductor
Taiyo Yuden CBC3225T4R7M
S2, S3, S5
S6, S7, S8
S9, S10
TP3, TP20
U1, U2, U4
3
3
2
2
3
S1
18
6
6
3
1
150
49.9
332
10k
DESCRIPTION
±1%
resistors (0402)
±1%
resistors (0402)
±1%
resistors (0603)
±1%
resistors (0603)
35
0.1μF
±10%
ceramic capacitors
(0402)
Switch, momentary, SPST-NO
Panasonic EVQQ2S02W
Switches, slide, SPDT
Copal Electronics CUS-12TB
Switches, slide, SP4T
Copal Electronics CUS-14TB
Switches, slide, SP3T
Copal Electronics CUS-13TB
Test points
Keystone 5000
Dual inverters (6 SC-70)
TI SN74LVC2G14DCKR
Low-jitter, frequency synthesizer
with selectable input reference
(56 TQFN)
Maxim MAX3673ETN+
Microsemi MAX3673ETN+
PCB: MAX3673 EV Kit+ Circuit
Board, Rev A
24
U7
1
2
1
None
1
________________________________________________________________
Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
MAX3673 Evaluation Kit
Evaluates: MAX3673
Quick Start
1) Set the slide switches to the following settings:
PLL_BYPASS = NORMAL
SEL_CLK = REFCLK0
DM = 61.44M
DA = 122.88M
DB = 122.88M
OUTA_EN
= A0, A1
OUTB_EN
= B0
FB_SEL = INTERNAL
2) Connect a +3.3V supply to VCC (J13) and GND
(J4). Set the supply current limit to 450mA.
3) Using SMA cables, connect a low-jitter 61.44MHz
differential clock source to the REFCLK0 input.
Verify that the green LEDs switch on for
IN0FAIL
and
LOCK.
4) Using SMA cables, connect the OUTA0 output to
test equipment. Terminate all unused enabled out-
puts (OUTB0 and OUTA1).
Detailed Description
The MAX3673 EV kit simplifies evaluation by providing
the hardware needed to evaluate all the MAX3673
functions. Table 1 contains functional descriptions for
the switches and indicators.
Clock Inputs
The clock inputs (REFCLK0, REFCLK1, FB_IN) are AC-
coupled at the SMA connectors and have on-board
100Ω differential terminations. For optimal jitter perfor-
mance it is critical to use a low-jitter, differential,
square-wave clock source. If such a source is not avail-
able, the clock inputs can be driven with a single-
ended sinusoidal or square-wave clock source for
functional testing.
Clock Outputs
The clock outputs (OUTA[3:0], OUTB[4:0]) have on-
board DC-biasing and are AC-coupled at the SMA con-
nectors to allow direct connection to 50Ω-terminated
test equipment. Unused outputs should be disabled
(using switches S9 and S10) or have 50Ω terminations
placed on the SMA connectors.
Table 1. Switch and Indicator Descriptions
COMPONENT
S1
S2
S3
S5
S6
S7
S8
S9
S10
D1, D2
D3, D4
D7, D8
NAME
MASTER RESET
PLL_BYPASS
SEL_CLK
FB_SEL
DM
DA
DB
OUTA_EN
OUTB_EN
IN0FAIL
IN1FAIL
LOCK
FUNCTION
Momentary switch to reset internal dividers. Not required at power-up. If the output divider
settings (DA, DB) are changed on the fly, a reset is required to phase align the outputs.
Selects normal PLL operation or PLL bypass.
Selects the reference clock input.
Selects internal or external feedback for the PLL. If external is selected, connect any of the
A-group or B-group outputs to the FB_IN input. If DA DB, a B-group output must be used.
Selects the frequency of the reference clock inputs.
Selects the frequency of the A-group clock outputs.
Selects the frequency of the B-group clock outputs.
Selects which A-group outputs are enabled (see Note).
Selects which B-group outputs are enabled (see Note).
REFCLK0 failure indicator (green = pass, red = fail).
REFCLK1 failure indicator (green = pass, red = fail).
PLL lock indicator (green = PLL locked, red = PLL not locked).
Note:
Setting
OUTA_EN
= “—” and
OUTB_EN
= “B0” at the same time enables a factory test mode and is not a valid mode of operation.
2
_______________________________________________________________________________________
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
