AR0141CS
1/4‐inch Digital Image
Sensor
Description
The ON Semiconductor AR0141CS is a 1/4−inch CMOS digital
image sensor with an active−pixel array of 1280 H x 800 V. It captures
images in linear mode, with a rolling−shutter readout. It includes
sophisticated camera functions such as in−pixel binning, windowing
and both video and single frame modes. It is designed for low light
scene performance. It is programmable through a simple two−wire
serial interface. The AR0141CS produces extraordinarily clear, sharp
digital pictures, and its ability to capture both continuous video and
single frames makes it the perfect choice for a wide range of
applications, including surveillance and HD video.
Table 1. KEY PERFORMANCE PARAMETERS
Parameter
Optical Format
Active Pixels
Pixel Size
Color Filter Array
Shutter Type
Input Clock Range
Output Clock Maximum
Output
Serial
Parallel
Frame Rate
720p
Responsivity
SNR
MAX
Maximum Dynamic Range
Supply Voltage
I/O
Digital
Analog
HiSPi
Power Consumption (Typical)
Operating Temperature (Ambient) T
A
Package Options
1/4-inch
1280 (H)
×
800 (V) (Entire Array)
3.0
mm
×
3.0
mm
RGB Bayer, Monochrome, RGB−IR
Electronic Rolling Shutter and GRR
6 – 50 MHz
148.5 Mp/s (4−lane HiSPi)
74.25 Mp/s (Parallel)
HiSPi, 12−bit
10-, 12-bit
60 fps
4.0 V/lux−sec
41 dB
Up to 79 dB
1.8 or 2.8 V
1.8 V
2.8 V
0.3 V
−
0.6 V, 1.7 V
−
1.9 V
326 mW (Linear Mode
1280 x 720 60 fps)
–30°C to +70°C
9 x 9 mm 63−ball iBGA
Typical Value
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IBGA63 9
y
9
CASE 503AH
ORDERING INFORMATION
See detailed ordering and shipping information on page 2 of
this data sheet.
Features
•
Superior Low-light Performance
•
Latest 3.0
mm
Pixel with ON Semiconductor
•
•
•
•
•
•
•
•
•
•
DR−Pix Technology
Linear Range Capture
1.0 Mp and 720p (16:9) Images
Support for External Mechanical Shutter
Support for External LED or Xenon Flash
On−chip Phase−locked Loop (PLL)
Oscillator
Integrated Position−based Color and Lens
Shading Correction
Slave Mode for Precise Frame−rate Control
Stereo/3D Camera Support
Statistics Engine
Data Interfaces: Four−lane Serial
High−speed Pixel Interface (HiSPi)
Differential signaling (SLVS and HiVCM),
or Parallel
Auto Black Level Calibration
High−speed Context Switching
Temperature Sensor
Video Surveillance
Scanning
Industrial
Stereo Vision
720p60 Video Applications
Publication Order Number:
AR0141CS/D
•
•
•
•
•
•
•
•
Applications
©
Semiconductor Components Industries, LLC, 2015
October, 2017
−
Rev. 7
1
AR0141CS
ORDERING INFORMATION
Table 2. AVAILABLE PART NUMBERS
Part Number
AR0141CS2C00SUEA0−DP
AR0141CS2C00SUEA0−DR
AR0141CS2C00SUEAD3−GEVK
AR0141CS2C00SUEAH−GEVB
AR0141CS2M00SUEA0
−
TPBR
AR0141CS2M00SUEA0
−
DPBR
AR0141CS2M00SUEAD3−GEVK
AR0141CS2M00SUEAH−GEVB
AR0141IRSH00SUEA0−DR
AR0141IRSH00SUEA0D3−GEVK
AR0141IRSH00SUEA0H3−GEVB
AR0141CSSM21SUEA0−TPBR
Product Description
Color iBGA
Color iBGA
Color iBGA Demo3 Kit
Color iBGA Headboard
Mono iBGA
Mono iBGA
Mono iBGA Demo3 Kit
Mono iBGA Headboard
RGB−IR, iBGA, Production
RGB−IR, Demo3 Kit
RGB−IR, Head Board
Mono, iBGA, 21 Deg Shift
Engineering Sample
Dry Pack without Protective Film
Tape and Reel with Protective Film
Dry Pack with Protective Film
Orderable Product Attribute Description
Dry Pack with Protective Film
Dry Pack without Protective Film
See the ON Semiconductor Device Nomenclature
document (TND310/D) for a full description of the naming
convention used for image sensors. For reference
documentation, including information on evaluation kits,
please visit our web site at
www.onsemi.com.
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2
AR0141CS
GENERAL DESCRIPTION
The ON Semiconductor AR0141CS can be operated in its
default mode or programmed for frame size, exposure, gain,
and other parameters. The default mode output is a
720p−resolution image at 60 frames per second (fps). In
linear mode, it outputs 12−bit raw data, using either the
parallel or serial (HiSPi) output ports. The device may be
operated in video (master) mode or in single frame trigger
mode.
FRAME_VALID and LINE_VALID signals are output on
dedicated pins, along with a synchronized pixel clock in
parallel mode.
The AR0141CS includes additional features to allow
application−specific tuning: windowing and offset, auto
black level correction, and on−board temperature sensor.
Optional register information and histogram statistic
information can be embedded in the first and last 2 lines of
the image frame.
FUNCTIONAL OVERVIEW
The AR0141CS is a progressive−scan sensor that
generates a stream of pixel data at a constant frame rate. It
uses an on−chip, phase−locked loop (PLL) that can be
optionally enabled to generate all internal clocks from a
ADC data
12
single master input clock running between 6 and 50 MHz.
The maximum output pixel rate is 148.5 Mp/s,
corresponding to a clock rate of 74.25 MHz. Figure 1 shows
a block diagram of the sensor.
Row noise correction
Black level correction
Test pattern generator
12 bits
Pixel defect correction
Adaptive CD filter
Parallel
12
HiSPi
12 or 10 bits
Digital gain and
pedestal
Figure 1. Block Diagram
User interaction with the sensor is through the two−wire
serial bus, which communicates with the array control,
analog signal chain, and digital signal chain. The core of the
sensor is a 1.1 Mp Active− Pixel Sensor array. The timing
and control circuitry sequences through the rows of the
array, resetting and then reading each row in turn. In the time
interval between resetting a row and reading that row, the
pixels in the row integrate incident light. The exposure is
controlled by varying the time interval between reset and
readout. Once a row has been read, the data from the
columns is sequenced through an analog signal chain
(providing offset correction and gain), and then through an
analog−to−digital converter (ADC). The output from the
ADC is a 12−bit value for each pixel in the array. The ADC
output passes through a digital processing signal chain
(which provides further data path corrections and applies
digital gain).
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3
AR0141CS
Digital Digital
I/O
Core
Power
1
Power
1
HiSPi
PLL Analog Analog
1
Power
1
Power
1
Power
1
Power
1.5 kW
2
1.5 kW
2
V
DD
_SLVS
V
DD
_IO
V
DD
V
DD
_PLL
V
AA
V
AA
_PIX
SLVS0_P
SLVS0_N
SLVS1_P
SLVS1_N
SLVS2_P
SLVS2_N
SLVS3_P
SLVS3_N
SLVSC_P
SLVSC_N
FLASH
SHUTTER
Master Clock
(6
−
50 MHz)
EXTCLK
S
ADDR
S
DATA
S
CLK
TRIGGER
OE_BAR
RESET_BAR
TEST
D
GND
To Controller
From Controller
A
GND
V
DD
_IO
V
DD
V
DD
_SLVS
V
DD
_PLL
V
AA
V
AA
_PIX
Digital
Ground
Analog
Ground
Notes:
1. All power supplies must be adequately decoupled.
2. ON Semiconductor recommends a resistor value of 1.5 kW, but a greater value may be used for slower two−wire speed.
3. The parallel interface output pads can be left unconnected if the serial output interface is used.
4. ON Semiconductor recommends that 0.1
mF
and 10
mF
decoupling capacitors for each power supply are mounted as
close as possible to the pad. Actual values and results may vary depending on layout and design considerations.
Check the AR0141CS demo headboard schematics for circuit recommendations.
5. ON Semiconductor recommends that analog power planes are placed in a manner such that coupling with the digital
power planes is minimized.
6. I/O signals voltage must be configured to match V
DD
_IO voltage to minimize any leakage currents.
Figure 2. Typical Configuration: Serial Four−Lane HiSPi Interface
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4
AR0141CS
Digital Digital
I/O
Core
Power
1
Power
1
PLL Analog Analog
Power
1
Power
1
Power
1
1.5 kW
2
1.5 kW
2
V
DD
_IO
V
DD
V
DD
_PLL
V
AA
V
AA
_PIX
Master Clock
(6
−
50 MHz)
EXTCLK
S
ADDR
S
DATA
S
CLK
TRIGGER
OE_BAR
RESET_BAR
TEST
D
GND
D
OUT
[11:0]
PIXCLK
LINE_VALID
FRAME_VALID
FLASH
SHUTTER
To Controller
From Controller
A
GND
V
DD
_IO
V
DD
V
DD
_PLL
V
AA
V
AA
_PIX
Digital
Ground
Analog
Ground
Notes:
1. All power supplies must be adequately decoupled.
2. ON Semiconductor recommends a resistor value of 1.5 kW, but a greater value may be used for slower two−wire speed.
3. The serial interface output pads and V
DD
_SLVS can be left unconnected if the parallel output interface is used.
4. ON Semiconductor recommends that 0.1
mF
and 10
mF
decoupling capacitors for each power supply are mounted as
close as possible to the pad. Actual values and results may vary depending on layout and design considerations.
Check the AR0141CS demo headboard schematics for circuit recommendations.
5. ON Semiconductor recommends that analog power planes are placed in a manner such that coupling with the digital
power planes is minimized.
6. I/O signals voltage must be configured to match V
DD
_IO voltage to minimize any leakage current.
7. The EXTCLK input is limited to 6−50 MHz.
Figure 3. Typical Configuration: Parallel Pixel Data Interface
Table 3. BALL DESCRIPTIONS, 9 X 9 MM, 63−BALL iBGA
Name
SLVS0_N
SLVS0_P
SLVS1_N
SLVS1_P
STANDBY
V
DD
_PLL
SLVSC_N
SLVSC_P
SLVS2_N
SLVS2_P
iBGA Pin
A2
A3
A4
A5
A8
B1
B2
B3
B4
B5
Type
Output
Output
Output
Output
Input
Power
Output
Output
Output
Output
Description
HiSPi serial data, lane 0, differential N
HiSPi serial data, lane 0, differential P
HiSPi serial data, lane 1, differential N
HiSPi serial data, lane 1, differential P
Standby (active high)
PLL power
HiSPi serial DDR clock differential N
HiSPi serial DDR clock differential P
HiSPi serial data, lane 2, differential N
HiSPi serial data, lane 2, differential P
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