USER’S MANUAL
ISL8117DEMO2Z
Demonstration Board User Guide
UG021
Rev 0.00
April 20, 2015
Description
The ISL8117DEMO2Z demonstration board (shown in
Figure 1)
features the
ISL8117.
The ISL8117 is a 60V high voltage
synchronous buck controller that offers external soft-start,
independent enable functions and integrates UV/OV/OC/OT
protection. Its current mode control architecture and internal
compensation network keep peripheral component count
minimal. Programmable switching frequency ranging from
100kHz to 2MHz helps to optimize inductor size while the
strong gate driver delivers up to 30A for the buck output.
Key Features
• Small, compact design
• Wide input range: 18V to 60V
• High light-load efficiency in pulse skipping DEM operation
• Programmable soft-start
• Optional DEM/CCM operation
• Supports prebias output with SR soft-start
• External frequency sync
• PGOOD indicator
• OCP, OVP, OTP, UVP protection
Specifications
The ISL8117DEMO2Z demonstration board is designed for
high current applications. The current rating of the
ISL8117DEMO2Z is limited by the FETs and inductor selected.
The ISL8117 gate driver is capable of delivering up to 20A for
the buck output as long as the proper FETs and inductor are
provided. The electrical ratings of ISL8117DEMO2Z are shown
in
Table 1.
TABLE 1. ELECTRICAL RATINGS
PARAMETER
Input Voltage
18V to 60V
RATING
References
• The
ISL8117
datasheet
Ordering Information
PART NUMBER
ISL8117DEMO2Z
DESCRIPTION
High Voltage PWM Step-Down
Synchronous Buck Controller
Switching Frequency 200kHz
Output Voltage
Output Current
OCP Set Point
12V
20A
Minimum 25A at ambient room temperature
Recommended Testing
Equipment
The following materials are recommended to perform testing:
• 0V to 60V power supply with at least 30A source current
capability
• Electronic loads capable of sinking current up to 30A
• Digital Multimeters (DMMs)
• 100MHz quad-trace oscilloscope
FIGURE 1. ISL8117DEMO2Z DEMONSTRATION BOARD TOP
FIGURE 2. ISL8117DEMO2Z DEMONSTRATION BOARD BOTTOM
UG021 Rev 0.00
April 20, 2015
Page 1 of 13
ISL8117DEMO2Z
Quick Test Guide
1. Jumper J5 provides the option to select CCM or DEM. Please
refer to
Table 2
for the desired operating option. Ensure that
the circuit is correctly connected to the supply and electronic
loads prior to applying any power. Please refer to
Figure 4
for
proper set-up.
2. Turn on the power supply.
3. Adjust input voltage V
IN
within the specified range and
observe output voltage. The output voltage variation should
be within 3%.
4. Adjust load current within the specified range and observe
output voltage. The output voltage variation should be
within 3%.
5. Use an oscilloscope to observe output voltage ripple and
phase node ringing. For accurate measurement, please refer
to
Figure 3
for proper test set-up.
TABLE 2.
JUMPER #
J5
POSITION
CCM (pins 1-2)
DEM (pins 2-3)
J6
(Pins 1-2)
FUNCTION
Continuous current mode
Diode emulation mode
Disable the PWM
The rated load current is 20A with the OCP point set at minimum
25A at room temperature ambient conditions.
The temperature operating range is -40°C to +125°C.
Please note that air flow is needed for higher temperature
ambient conditions.
Evaluating the Other Output
Voltages
The ISL8117DEMO2Z kit output is preset to 12V, however, the
output can be adjusted from 5V to 24V. The output voltage
programming resistor, R
2
, will depend on the desired output
voltage of the regulator and the value of the feedback resistor
R
1
, as shown in
Equation 1.
0.6
-
R
2
=
R
1
-----------------------------
V
OUT
–
0.6
(EQ. 1)
Table 3
shows the component selection that should be used for
the respective V
OUT
of 5V, 12V and 24V.
TABLE 3. EXTERNAL COMPONENT SELECTION
V
OUT
5V
R
2
5.9k
R
4
R
7
L
1
C
6
V
IN
MAX
RANGE I
OUT
8V~60V 20A
36k 7.5k IHLP6767GZER3R3M11, 150pF
3.3µH/35A
12V 2.26k 90.9k 7.5k IHLP6767GZER5R6M11, 220pF 18V~60V 20A
5.6µH/28A
24V 1.1k 150k 3.3k IHLP6767GZER100M11, 470pF 28V~60V 10A
10µH/19A
OUTPUT CAP
OUTPUT CAP
OUTPUT CAP
OR MOSFET
OR MOSFET
Layout Guidelines
Careful attention to layout requirements is necessary for
successful implementation of an ISL8117 based DC/DC
converter. The ISL8117 switches at a very high frequency and
therefore the switching times are very short. At these switching
frequencies, even the shortest trace has significant impedance.
Also, the peak gate drive current rises significantly in an
extremely short time. Transition speed of the current from one
device to another causes voltage spikes across the
interconnecting impedances and parasitic circuit elements.
These voltage spikes can degrade efficiency, generate EMI and
increase device overvoltage stress and ringing. Careful
component selection and proper PC board layout minimizes the
magnitude of these voltage spikes.
There are three sets of critical components in a DC/DC converter
using the ISL8117: the controller, the switching power
components and the small signal components. The switching
power components are the most critical from a layout point of
view because they switch a large amount of energy which tends
to generate a large amount of noise. The critical small signal
components are those connected to sensitive nodes or those
supplying critical bias currents. A multilayer printed circuit board
is recommended.
FIGURE 3. PROPER PROBE SET-UP TO MEASURE OUTPUT RIPPLE
AND PHASE NODE RINGING
Functional Description
The ISL8117DEMO2Z is a compact design with high efficiency
and high power density.
As shown in
Figure 4
on
page 3,
18V to 60V V
IN
is supplied to J1
(+) and J2 (-). The regulated 12V output on J3 (+) and J4 (-) can
supply up to 20A to the load. Due to high thermal efficiency, the
demonstration board can run at 20A continuously without air
flow in room temperature ambient condition.
As shown in
Table 2,
connector J5 provides selection of either
CCM mode (shorting pin 1 and pin 2) or DEM mode (shorting
pin 2 and pin 3). Connector J6 provides an option to disable the
converter by shorting its pin 1 and pin 2.
Operating Range
The input voltage range is from 18V to 60V for an output voltage
of 12V. If the output voltage is set to a lower value, the minimum
V
IN
can be reset to a lower value by changing the ratio of R
4
and
R
5
. The minimum EN threshold that V
IN
can be set to is 4.5V.
UG021 Rev 0.00
April 20, 2015
Page 2 of 13
ISL8117DEMO2Z
Layout Considerations
1. The input capacitors, upper FET, lower FET, inductor and
output capacitor should be placed first. Isolate these power
components on dedicated areas of the board with their
ground terminals adjacent to one another. Place the input
high frequency decoupling ceramic capacitors very close to
the MOSFETs.
2. If signal components and the IC are placed in a separate area
to the power train, it is recommend to use full ground planes
in the internal layers with shared SGND and PGND to simplify
the layout design. Otherwise, use separate ground planes for
power ground and small signal ground. Connect the SGND
and PGND together close to the IC. DO NOT connect them
together anywhere else.
3. The loop formed by the input capacitor, the top FET and the
bottom FET must be kept as small as possible.
4. Ensure the current paths from the input capacitor to the
MOSFET, to the output inductor and the output capacitor are
as short as possible with maximum allowable trace widths.
5. Place the PWM controller IC close to the lower FET. The LGATE
connection should be short and wide. The IC can be best
placed over a quiet ground area. Avoid switching ground loop
currents in this area.
6. Place VCC5V bypass capacitor very close to the VCC5V pin of
the IC and connect its ground to the PGND plane.
7. Place the gate drive components - optional BOOT diode and
BOOT capacitors - together near the controller IC.
8. The output capacitors should be placed as close to the load as
possible. Use short wide copper regions to connect output
capacitors to load to avoid inductance and resistances.
9. Use copper filled polygons or wide but short trace to connect
the junction of upper FET, lower FET and output inductor. Also
keep the PHASE node connection to the IC short. DO NOT
unnecessarily oversize the copper islands for the PHASE
node. Since the phase nodes are subjected to very high dv/dt
voltages, the stray capacitor formed between these islands
and the surrounding circuitry will tend to couple switching
noise.
10. Route all high speed switching nodes away from the control
circuitry.
11. Create a separate small analog ground plane near the IC.
Connect the SGND pin to this plane. All small signal grounding
paths including feedback resistors, current limit setting
resistor, soft starting capacitor and EN pull-down resistor
should be connected to this SGND plane.
12. Separate the current sensing trace from the PHASE node
connection.
13. Ensure the feedback connection to the output capacitor is
short and direct.
A
V
O
+
-
+
V
IN
V
-
LOAD
+
A
-
FIGURE 4. PROPER TEST SET-UP
.
UG021 Rev 0.00
April 20, 2015
Page 3 of 13
ISL8117DEMO2Z
Typical Demonstration Board Performance Curves
otherwise noted.
100
95
90
EFFICIENCY (%)
EFFICIENCY (%)
85
80
V
IN
= 48V
75
70
65
60
0
2
4
6
8
10
I
OUT
(A)
12
14
16
18
20
V
IN
= 24V
100
95
90
85
80
75
70
65
60
0
2
4
6
V
IN
= 48V
V
IN
= 48V, V
OUT
= 12V, unless
V
IN
= 24V
8
10
I
OUT
(A)
12
14
16
18
20
FIGURE 5. CCM EFFICIENCY vs LOAD, V
OUT
= 5V
FIGURE 6. DEM EFFICIENCY vs LOAD, V
OUT
= 5V
5.090
5.085
5.080
5.075
5.070
5.065
V
IN
= 48V
5.060
5.055
5.050
0
2
4
6
8
10
I
OUT
(A)
12
14
16
18
20
V
IN
= 24V
V
OUT
(V)
FIGURE 7. LOAD REGULATION, V
OUT
= 5V
1.00
0.95
0.90
EFFICIENCY
0.85
0.80
V
IN
= 18V
0.75
0.70
0.65
0.60
0
2
4
6
8
10
I
OUT
(A)
12
14
16
18
20
V
IN
= 48V
V
IN
= 36V
V
IN
= 24V
EFFICIENCY
V
IN
= 60V
1.00
0.95
0.90
0.85
0.80
0.75
0.70
0.65
0.60
0
2
4
6
8
10
I
OUT
(A)
12
14
16
18
20
V
IN
= 36V
V
IN
= 24V
V
IN
= 18V
V
IN
= 48V
V
IN
= 60V
FIGURE 8. CCM EFFICIENCY vs LOAD
FIGURE 9. DEM EFFICIENCY vs LOAD
UG021 Rev 0.00
April 20, 2015
Page 4 of 13
ISL8117DEMO2Z
Typical Demonstration Board Performance Curves
otherwise noted. (Continued)
12.29
12.27
12.25
V
OUT
(V)
12.23
V
IN
= 36V
12.21
12.19
12.17
12.15
V
IN
= 24V
V
IN
= 18V
12.25
V
OUT
(V)
12.23
12.29
12.27
V
IN
= 48V, V
OUT
= 12V, unless
I
O
= 10A
I
O
= 0A
V
IN
= 48V
V
IN
= 60V
I
O
= 20A
12.21
12.19
12.17
12.15
18
2
4
6
8
10
12
14
16
18
20
23
28
33
38
V
IN
(V)
43
48
53
58
I
OUT
(A)
FIGURE 10. CCM MODE LOAD REGULATION
FIGURE 11. CCM MODE LINE REGULATION
10.00
PHASE 50V/DIV
LGATE 5V/DIV
1.00
I
IN
(A)
CCM
0.10
I
L
5A/DIV
DEM
0.01
0.01
0.1
I
OUT
(A)
1
10
2µs/DIV
CLKOUT 5V/DIV
FIGURE 12. INPUT CURRENT COMPARISON WITH MODE = CCM/DEM
FIGURE 13. PHASE, LGATE, CLKOUT AND INDUCTOR CURRENT
WAVEFORMS
, V
IN
= 48V,
I
O
= 0A
V
OUT
50mV/DIV, V
IN
= 48V, I
O
= 0A
V
OUT
50mV/DIV, V
IN
= 48V, I
O
= 0A
1ms/DIV
V
OUT
50mV/DIV, V
IN
= 48V, I
O
= 20A
V
OUT
50mV/DIV, V
IN
= 48V, I
O
= 20A
4µs/DIV
4µs/DIV
FIGURE 14. OUTPUT RIPPLE, CCM MODE
FIGURE 15. OUTPUT RIPPLE, DEM MODE
UG021 Rev 0.00
April 20, 2015
Page 5 of 13
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