ST16C550
UART WITH 16-BYTE FIFO’s
April 2005
GENERAL DESCRIPTION
The ST16C550 (550) is a universal asynchronous re-
ceiver and transmitter with 16 byte transmit and receive
FIFO. It operates at 2.97 to 5.5 volts. A programmable
baud rate generator can select transmit and receive
clock rates from 50 bps to 1.5 Mbps.
The ST16C550 is an improved version of the NS16C550
UART with higher operating speed and lower access
time. The ST16C550 on board status registers provides
the error conditions, type and status of the transfer
operation being performed. Included is complete MO-
DEM control capability, and a processor interrupt
system that may be software tailored to the user’s
requirements. The ST16C550 provides internal loop-
back capability for on board diagnostic testing.
The ST16C550 is available in 40 pin PDIP, 44 pin PLCC,
and 48 pin TQFP packages. It is fabricated in an
advanced CMOS process to achieve low drain power
and high speed requirements.
PLCC Package
-DSR
41
-CTS
40
39
38
37
36
35
VCC
N.C.
-CD
42
-RI
43
D4
D3
D2
D1
D0
D5
D6
D7
RCLK
RX
N.C.
TX
CS0
CS1
-CS2
-BAUDOUT
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
44
6
5
4
3
2
1
RESET
-OP1
-DTR
-RTS
-OP2
N.C.
INT
-RXRDY
A0
A1
A2
ST16C550CJ44
34
33
32
31
30
29
XTAL1
XTAL2
-IOW
-IOR
-TXRDY
FEATURES
•
Pin to pin and functionally compatible to the Industry
Standard 16C550
•
2.97 to 5.5 volt operation
•
24MHz clock operation at 5V
•
16MHz clock operation at 3.3V
•
16 byte transmit FIFO
•
16 byte receive FIFO with error flags
•
Full duplex operation
•
Transmit and receive control
•
Four selectable receive FIFO interrupt trigger levels
•
Standard modem interface
•
Compatible with ST16C450
•
Low operating current ( 1.2mA typ.)
ORDERING INFORMATION
Part number
Package
Operating temperature
Device Status
ST16C550CP40
ST16C550CJ44
ST16C550CQ48
ST16C550IP40
ST16C550IJ44
ST16C550IQ48
40-Lead
44-Lead
48-Lead
40-Lead
44-Lead
48-Lead
PDIP
PLCC
TQFP
PDIP
PLCC
TQFP
0° C to + 70° C
0° C to + 70° C
0° C to + 70° C
-40° C to + 85° C
-40° C to + 85° C
-40° C to + 85° C
Active. See the ST16C550CQ48 for new designs.
Active
Active
Active. See the ST16C550IQ48 for new designs.
Active
Active
Rev. 5.01
EXAR
Corporation, 48720 Kato Road, Fremont, CA 94538
•
(510) 668-7000
•
FAX (510) 668-7017
-DDIS
IOW
GND
N.C.
IOR
-AS
ST16C550
Figure 1, PACKAGE DESCRIPTION, ST16C550
48 Pin TQFP Package
-DSR
-CTS
VCC
40 Pin DIP Package
N.C.
N.C.
-CD
-RI
D4
D3
D2
D1
D0
D0
D1
D2
1
2
3
4
5
6
7
40
39
38
37
36
35
34
VCC
-RI
-CD
-DSR
-CTS
RESET
-OP1
-DTR
-RTS
-OP2
INT
-RXRDY
A0
A1
A2
-AS
-TXRDY
-DDIS
IOR
-IOR
48
47
46
45
44
43
42
41
40
39
38
37
N.C.
D5
D6
D7
RCLK
N.C.
RX
TX
CS0
CS1
-CS2
-BAUDOUT
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
36
35
34
33
32
N.C.
RESET
D3
D4
-OP1
-DTR
-RTS
-OP2
INT
-RXRDY
A0
A1
A2
D5
D6
D7
RCLK
RX
TX
CS0
CS1
ST16C550CQ48
31
30
29
28
27
26
25
8
9
10
11
12
13
14
15
16
17
18
19
20
ST16C550CP40
33
32
31
30
29
28
27
26
25
24
23
22
21
N.C.
-CS2
-BAUDOUT
XTAL1
XTAL2
-IOW
IOW
GND
N.C.
GND
-IOR
XTAL1
XTAL2
-IOW
N.C.
IOW
IOR
Rev. 5.01
2
-TXRDY
-DDIS
-AS
ST16C550
Figure 2, BLOCK DIAGRAM
D0-D7
-IOR,IOR
-IOW,IOW
RESET
Data bus
&
Control Logic
Transmit
FIFO
Registers
Transmit
Shift
Register
TX
Inter Connect Bus Lines
&
Control signals
Receive
FIFO
Registers
Receive
Shift
Register
RX
A0-A2
-AS
CS0,CS1
-CS2
-DDIS
Register
Select
Logic
-DTR,-RTS
-OP1,-OP2
Clock
&
Baud Rate
Generator
Interrupt
Control
Logic
Modem
Control
Logic
-CTS
-RI
-CD
-DSR
INT
-RXRDY
-TXRDY
Rev. 5.01
3
XTAL1
RCLK
XTAL2
-BAUDOUT
ST16C550
SYMBOL DESCRIPTION
Symbol
40
A0
A1
A2
IOR
28
27
26
22
Pin
44
31
30
29
25
48
28
27
26
20
Signal
type
I
I
I
I
Pin Description
Address-0 Select Bit Internal registers address selection.
Address-1 Select Bit Internal registers address selection.
Address-2 Select Bit Internal registers address selection.
Read data strobe. Its function is the same as -IOR (see -
IOR), except it is active high. Either an active -IOR or IOR
is required to transfer data from 16C550 to CPU during a
read operation. Connect to logic 0 when using -IOR.
Chip Select-0. Logical 1 on this pin provides the chip select-
0 function. Connect CS0 to logic 1 if using CS1 or -CS2.
Chip Select-1. Logical 1 on this pin provides the chip select-
1 function. Connect CS1 to logic 1 if using CS0 or -CS2.
Chip Select -2. Logical 0 on this pin provides the chip select-
2 function. Connect to logic 0 if using CS0 or CS1.
Write data strobe. Its function is the same as -IOW (see -
IOW), but it acts as an active high input signal. Either -IOW
or IOW is required to transfer data from the CPU to
ST16C550 during a write operation. Connect to logic 0 when
using -IOW.
Address Strobe. A logic 1 transition on -AS latches the state
of the chip selects and the register select bits, A0-A2. This
input is used when address and chip selects are not stable
for the duration of a read or write operation, i.e., a micropro-
cessor that needs to de-multiplex the address and data bits.
If not required, the -AS input can be permanently tied to a
logic 0.
CS0
12
14
9
I
CS1
13
15
10
I
-CS2
14
16
11
I
IOW
19
21
17
I
-AS
25
28
24
I
D0-D7
1-8
2-9
43-47
2-4
I/O
Data Bus (Bi-directional) - These pins are the eight bit, tri-
state data bus for transferring information to or from the
controlling CPU. D0 is the least significant bit and the first
data bit in a transmit or receive serial data stream.
Signal and Power Ground.
GND
20
22
18
Pwr
Rev. 5.01
4
ST16C550
SYMBOL DESCRIPTION
Symbol
40
-IOR
21
Pin
44
24
48
19
Signal
type
I
Pin Description
Read data strobe (active low strobe). A logic 0 on this pin
transfers the contents of the ST16C550 data bus to the CPU.
Connect to logic 1 when using IOR.
Write data strobe (active low strobe). A logic 0 on this pin
transfers the contents of the CPU data bus to the addressed
internal register. Connect to logic 1 when using IOW.
Interrupt Request (active high). Interrupts are enabled in the
interrupt enable register (IER), and when an interrupt con-
dition exists. Interrupt conditions include: receiver errors,
available receiver buffer data, transmit buffer empty, or
when a modem status flag is detected.
Receive Ready. When operating in the FIFO mode, one of
two types of DMA signaling can be selected using the FIFO
control register bit-3. When operating in the ST16C450
mode, only DMA mode “0” is allowed. Mode “0” supports
single transfer DMA in which a transfer is made between
CPU bus cycles. Mode “1” supports multi-transfer DMA in
which multiple transfers are made continuously until the
receiver FIFO has been emptied. In DMA mode “0” -RXRDY
is low, when there is at least one character in the receiver
FIFO or receive holding register. In DMA mode “1”, -RXRDY
is low, when the trigger level or the time-out has been
reached.
Transmit Ready. When operating in the FIFO mode, one of
two types of DMA signaling can be selected using the FIFO
control register bit-3. When operating in the ST16C450
mode, only DMA mode “0” is allowed. Mode “0” supports
single transfer DMA in which a transfer is made between
CPU bus cycles. Mode “1” supports multi-transfer DMA in
which multiple transfers are made continuously until the
transmit FIFO has been filled.
Baud Rate Generator Output. This pin provides the 16X
clock of the selected data rate from the baud rate generator.
The RCLK pin must be connected externally to -BAUDOUT
when the receiver is operating at the same data rate.
-IOW
18
20
16
I
INT
30
33
30
O
-RXRDY
29
32
29
O
-TXRDY
24
27
23
O
-BAUDOUT
15
17
12
O
Rev. 5.01
5
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