ISL70003SEH
NOT RECOMMENDED FOR NEW DESIGNS
RECOMMENDED REPLACEMENT PART
ISL70003ASEH
DATASHEET
FN8604
Rev 6.00
December 8, 2016
Radiation Hardened and SEE Hardened 3V to 13.2V, 6A Buck Regulator
The
ISL70003SEH
is a radiation and SEE hardened
synchronous buck regulator capable of operating over an input
voltage range of 3.0V to 13.2V. With integrated MOSFETs, this
highly efficient single chip power solution provides a tightly
regulated output voltage that is externally adjustable from
0.6V to ~90% of the input voltage. Continuous output load
current capability is 6A for T
J
≤
+125°C and 3A for T
J
≤
+150°C.
The ISL70003SEH uses voltage mode control architecture with
feed-forward and switches at a selectable frequency of
500kHz or 300kHz. Loop compensation is externally
adjustable to allow for an optimum balance between stability
and output dynamic performance. The internal synchronous
power switches are optimized for high efficiency and excellent
thermal performance.
The chip features two logic-level disable inputs that can be
used to inhibit pulses on the phase (LXx) pins in order to
maximize efficiency based on the load current. The
ISL70003SEH also supports DDR applications and contains a
buffer amplifier for generating the V
REF
voltage.
High integration, best in class radiation performance and a
feature-filled design make the ISL70003SEH an ideal choice
to power many of todays small form-factor applications.
Features
• Acceptance tested to 50krad(Si) (LDR) wafer-by-wafer
• ±1% reference voltage over line, temperature, and radiation
• Integrated MOSFETs 31mΩ
PFET/21mΩ NFET
- 95% peak efficiency
• Externally adjustable loop compensation
• Supports DDR applications (V
TT
tracks V
DDQ
/2)
- Buffer amplifier for generating V
REF
voltage
- 3A current sinking capability
• Grounded lid eliminates charge build up
• IMON pin for output current monitoring
• Adjustable analog soft-start
• Diode emulation for increased efficiency at light loads
• 500kHz or 300kHz operating frequency synch wording
• Monotonic start-up into prebiased load
• Full military temperature range operation
- T
A
= -55°C to +125°C
- T
J
= -55°C to +150°C
• Radiation tolerance
- High dose rate (50-300rad(Si)/s). . . . . . . . . . . 100krad(Si)
- Low dose rate (0.01rad(Si)/s) . . . . . . . . . . . . 100krad(Si)*
* Limit established by characterization.
• SEE hardness
- SEB and SEL LET
TH
. . . . . . . . . . . . . . . . 86.4MeV•cm
2
/mg
- SET at LET 86.4MeV•cm
2
/mg . . . . . . . . . . . < ±3%
ΔV
OUT
- SEFI LET
TH
. . . . . . . . . . . . . . . . . . . . . . . . . 60MeV•cm
2
/mg
• Electrically screened to DLA SMD
5962-14203
Applications
• FPGA, CPLD, DSP, CPU core, and I/O supply voltages
• DDR memory supply voltages
• Low-voltage, high-density distributed power systems
TABLE 1. DIFFERENCES BETWEEN FAMILY OF PARTS
PART #
ISL70003SEH
ISL70003ASEH
OUTPUT
CURRENT
6A
9A
OUTPUT VOLTAGE
LOAD REGULATION
<2%
<1/2%
Related Literature
• For a full list of related documents, visit our website
-
ISL70003SEH
product page
100
95
90
85
80
75
70
65
60
55
50
EFFICIENCY (%)
5V
2.5V
3.3V
9V
0
1
2
3
4
LOAD CURRENT (A)
5
6
FIGURE 1. POWER DISTRIBUTION SOLUTION FOR RAD HARD LOW
POWER FPGA’s
FIGURE 2. EFFICIENCY vs LOAD, V
IN
= 12V, f
SW
= 300kHz ALL
OUTPUTS ACTIVE
FN8604 Rev 6.00
December 8, 2016
Page 1 of 32
ISL70003SEH
Table of Contents
Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Typical Application Schematics. . . . . . . . . . . . . . . . . . . . . . . . 7
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Thermal Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Recommended Operating Conditions . . . . . . . . . . . . . . . . . . 9
Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Typical Performance Curves . . . . . . . . . . . . . . . . . . . . . . . . .12
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Power Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Soft-Start. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Power-Good . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Fault Monitoring and Protection . . . . . . . . . . . . . . . . . . . . . .18
Undervoltage and Overvoltage Monitor. . . . . . . . . . . . . . . . . . 18
Undervoltage Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Overcurrent Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Voltage Feed-Forward . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Switching Frequency Selection . . . . . . . . . . . . . . . . . . . . . . . . 20
Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Output Voltage Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Setting the Overcurrent Protection Level . . . . . . . . . . . . . . . . 20
Disabling the Power Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
IMON Current-Sense Output . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Diode Emulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
DDR Application. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
DDR Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Derating Current Capability . . . . . . . . . . . . . . . . . . . . . . . . . 23
General Design Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output Inductor Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output Capacitor Selection . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input Capacitor Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Feedback Compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Modulator Break Frequency Equations . . . . . . . . . . . . . . . . .
Compensation Break Frequency Equations . . . . . . . . . . . . .
PCB Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PCB Plane Allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PCB Component Placement . . . . . . . . . . . . . . . . . . . . . . . . . .
LX Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Thermal Management for Ceramic Package . . . . . . . . . . . .
Lead Strain Relief . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Heatsink Mounting Guidelines . . . . . . . . . . . . . . . . . . . . . . . .
Heatsink Electrical Potential . . . . . . . . . . . . . . . . . . . . . . . . . .
Heatsink Mounting Materials . . . . . . . . . . . . . . . . . . . . . . . . .
23
23
23
24
25
25
25
26
26
26
26
26
26
26
26
26
Package Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Weight of Packaged Device . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Lid Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Die Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Die Dimensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Interface Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Layout Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Step and Repeat . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
About Intersil. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Package Outline Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
R64.A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
R64.C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
FN8604 Rev 6.00
December 8, 2016
Page 2 of 32
ISL70003SEH
Functional Block Diagram
VREFA
VREFD
VREF_OUTS
EN
POR_VIN
POR AND ON/OFF
CONTROL
LINEAR
REGULATORs
AVDD
DVDD
SEL1
RT/CT
RAMP
SEL2
IMON
CURRENT
SENSE
PVINx
SS_CAP
SOFT-
START
PWM
CONTROL
LOGIC
NI
FB
VERR
EA
COMP
GATE
DRIVE
LXx
PGOOD
REF
BUFIN-
BUFIN+
BUFOUT
SYNC
FSEL
DE
BUF
DDR VREF
BUFFER AMP
PWM
REFERENCE
0.6V
VOUT
MONITOR
SGND
PGNDx
OCSETA
OCSETB
OVERCURRENT
ADJUST
PGNDx
DGND
AGND
FIGURE 3. FUNCTIONAL BLOCK DIAGRAM
Ordering Information
ORDERING SMD
NUMBER (Note
1)
5962R1420301VXC
5962R1420301VYC
5962R1420301V9A
N/A
N/A
N/A
NOTES:
1. Specifications for Rad Hard QML devices are controlled by the Defense Logistics Agency Land and Maritime (DLA). The SMD numbers listed must be
used when ordering.
2. These Intersil Pb-free Hermetic packaged products employ 100% Au plate - e4 termination finish, which is RoHS compliant and compatible with both
SnPb and Pb-free soldering operations.
PART NUMBER
(Note
2)
ISL70003SEHVF
ISL70003SEHVFE
ISL70003SEHVX
ISL70003SEHF/PROTO
ISL70003SEHFE/PROTO
ISL70003SEHX/SAMPLE
TEMPERATURE
RANGE (°C)
-55 to +125
-55 to +125
-55 to +125
-55 to +125
-55 to +125
-55 to +125
PACKAGE
(RoHS COMPLIANT)
64 Ld CQFP
64 Ld CQFP with Heatsink
Die
64 Ld CQFP
64 Ld CQFP with Heatsink
Die
R64.A
R64.C
PACKAGE
DRAWING
R64.A
R64.C
FN8604 Rev 6.00
December 8, 2016
Page 3 of 32
ISL70003SEH
Pin Configuration
ISL70003SEH
(64 LD CQFP)
TOP VIEW
BUFOUT
OCSETB
OCSETA
BUFIN+
PGND1
PGND2
BUFIN-
PVIN2
PVIN1
REF
PVIN3
SGND
IMON
BOTTOM SIDE DETAIL
FOR PIN 1 LOCATION
NC/HS*
LX1
1 (NI)
NI
FB
1
2
3
4
5
6
7
8
9
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
48
47
46
45
44
43
42
41
40
39
38
37
36
HEATSINK OUTLINE
*
35
34
LX2
LX3
PGND3
PGND4
LX4
PVIN4
PVIN5
LX5
PGND5
PGND6
LX6
PVIN6
PVIN7
LX7
PGND7
PGND8
LX8
VERR
POR_VIN
VREFA
AVDD
AGND
DGND
VREF_OUTS
DVDD
VREFD
ENABLE
RT/CT
FSEL
SYNC
SS_CAP
PRODUCT BRAND
NAME AREA
(Note
3)
10
11
12
13
14
15
16
33
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
PVIN10
PVIN9
PGND10
PGOOD
PGND9
PVIN8
LX10
LX9
SEL1
SEL2
GND
GND
GND
GND
GND
DE
NOTE:
3. The ESD triangular mark is indicative of pin #1 location. It is part of the device marking and is
placed on the lid in the quadrant where pin #1 is located.
* Indicates heatsink package R64.C
FN8604 Rev 6.00
December 8, 2016
Page 4 of 32
ISL70003SEH
Pin Descriptions
PIN NUMBER
1
2
PIN NAME
NI
FB
ESD CIRCUIT
1
1
DESCRIPTION
This pin is the non-inverting input to the internal error amplifier. Connect this pin to the REF pin for
typical applications or the BUFOUT pin for DDR memory power applications.
This pin is the inverting input to the internal error amplifier. An external Type III compensation network
should be connected between this pin and the VERR pin. The connection between the FB resistor divider
and the output inductor should be a Kelvin connection to optimize performance.
This pin is the output of the internal error amplifier. An external compensation network should be
connected between this pin and the FB pin.
This pin is the power-on reset input to the IC. This is a comparator-type input with a rising threshold of
0.6V and programmable hysteresis. Driving this pin above 0.6V enables the IC. Bypass this pin to AGND
with a 10nF ceramic capacitor to mitigate SEE.
This pin is the output of the internal linear regulator and the bias supply input to the internal analog
control circuitry. Locally filter this pin to AGND using a 0.47µF ceramic capacitor as close as possible to
the IC.
This pin provides the supply for internal linear regulator of the ISL70003SEH. The supply to AVDD
should be locally bypassed using a ceramic capacitor. Tie AVDD to the PVINx pins.
This pin is the analog ground associated with the internal analog control circuitry. Connect this pin
directly to the PCB ground plane.
This pin is the ground associated with the internal digital control circuitry. Connect this pin directly to
the PCB ground plane.
This pin is the output of the internal linear regulator and the supply input to the internal reference
circuit. Locally filter this pin to AGND using a 0.47µF ceramic capacitor as close as possible to the IC.
This pin provides the supply for the internal linear regulator of the ISL70003SEH. The supply to DVDD
should be locally bypassed using a ceramic capacitor. Tie DVDD to the PVINx pin.
This pin is the output of the internal linear regulator and the bias supply input to the internal digital
control circuitry. Locally filter this pin to DGND using a 0.47µF ceramic capacitor as close as possible
to the IC.
This pin is a logic-level enable input. Pulling this pin low powers down the chip by placing it into a very
low power sleep mode.
A resistor to VIN and a capacitor to GND provide feed-forward to keep a constant modulator gain of 4.8
as VIN varies.
This pin is the oscillator frequency select input. Tie this pin to 5V to select a 300kHz nominal oscillator
frequency. Tie this pin to the PCB ground plane to select a 500kHz nominal oscillator frequency.
This pin is the frequency synchronization input to the IC. This pin should be tied to GND to free-run from
the internal oscillator or connected to an external clock for external frequency synchronization.
This pin is the soft-start input. Connect a ceramic capacitor from this pin to the PCB ground plane to set
the soft-start output ramp time in accordance with
Equation 1:
t
SS
=
C
SS
V
REF
I
SS
where:
t
SS
= soft-start output ramp time
C
SS
= soft-start capacitance
V
REF
= reference voltage (0.6V typical)
I
SS
= soft-start charging current (23µA typical)
Soft-start time is adjustable from approximately 2ms to 200ms. The range of the soft-start capacitor
should be 82nF to 8.2µF, inclusive.
17, 18, 19, 20, 21
22
GND
PGOOD
2
6
Connect this pin to the PCB ground plane.
This pin is the power-good output. This pin is an open-drain, logic output that is pulled to DGND when
the output voltage is outside a ±11% typical regulation window. This pin can be pulled up to any voltage
from 0V to 13.2V, independent of the supply voltage. A nominal 1kΩ to 10kΩ pull-up resistor is
recommended. Bypass this pin to the PCB ground plane with a 10nF ceramic capacitor to mitigate SEE.
(EQ. 1)
3
4
VERR
POR_VIN
1
1
5
VREFA
3
6
7
8
9
10
11
AVDD
AGND
DGND
VREF_OUTS
DVDD
VREFD
5
1, 3
2, 4
4
6
4
12
13
14
15
16
ENABLE
RT/CT
FSEL
SYNC
SS_CAP
6
6
2
2
2
FN8604 Rev 6.00
December 8, 2016
Page 5 of 32
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