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Cmod A7 Reference Manual
Revised June 24, 2016
This manual applies to the Cmod A7 Rev. B
Overview
The Digilent Cmod A7 is a small, 48-pin DIP form factor board built around a Xilinx Artix-7 FPGA. The board also
includes a USB-JTAG programming circuit, USB-UART bridge, clock source, Pmod host connector, SRAM, Quad-SPI
Flash, and basic I/O devices. These components make it a formidable, albeit compact, platform for digital logic
circuits and MicroBlaze™ embedded soft-core processor designs alike. There are 44 Digital FPGA I/O signals and
two FPGA Analog inputs that are routed to 100-mil-spaced through-hole pins so that users can integrate
programmable logic design directly into a solderless breadboard circuit. At just 0.7” by 2.75”, it can also be loaded
in a standard socket and used in embedded systems.
The Cmod A7.
System Features
o
512KB SRAM with an 8-bit bus and 8ns
access times
o
4MB Quad-SPI Flash
o
USB-JTAG Programming Circuitry
o
Powered from USB or external 3.3-5.5V
supply connected to DIP pins
System Connectivity
o
USB-UART bridge
Interaction and Sensory Devices
o
2 LEDs
o
1 RGB LED
o
2 Push Buttons
Expansion Connectors
o
48-pin DIP connector with 44 Digital I/O
and 2 Analog inputs (0-3.3V)
o
One Pmod connector with 8 Digital I/O
The Cmod A7 can be purchased with either an Artix-15T or Artix-35T FPGA. These two Cmod A7 product variants
are referred to as the Cmod A7-15T and Cmod A7-35T, respectively. When Digilent documentation describes
functionality that is common to both of these variants, they are referred to collectively as the “Cmod A7”. When
describing something that is only common to a specific variant, the variant will be explicitly called out by its name.
The only difference between the Cmod A7-15T and Cmod A7-35T are the capabilities of the FPGA found on the
board. They compare as follows:
DOC#: 502-328
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Other product and company names mentioned may be trademarks of their respective owners.
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Product Variant
FPGA Part
1 MSPS On-chip ADC
Programming options
Look-up Tables (LUTs)
Flip-Flops
Block RAM
Clock Management Tiles
Cmod A7-15T
XC7A15T-1CPG236C
Yes
Quad-SPI Flash/JTAG
10,400
20,800
112.5 KB
5
Cmod A7-35T
XC7A35T-1CPG236C
Yes
Quad-SPI Flash/JTAG
20,800
41,600
225 KB
5
The Cmod A7 is fully compatible with the high-performance Vivado® Design Suite. It is supported under the free
WebPACK™ license, so designs can be implemented at no additional cost. This free license includes the ability to
create MicroBlaze soft-core processor designs. Design resources, example projects, and tutorials are available for
download at the Cmod A7
Resource Center.
1
Power Supplies
The Cmod A7 uses a
Linear Technologies LTC3569
triple output buck power regulator to generate the needed
voltages for the onboard components. It is connected as shown in Fig. 1.1. The characteristics of the outputs are
shown in Table 1.1.
Figure 1.1. Cmod A7 Power Supply.
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Power
IC
Label
IC10
Net
name
Upstream
net name
Power IC
Type
Switching
PS
Switching
PS
Min/Typ/Max
Voltage
Max.
Current
Major Devices
and Connectors
FPGA Core and
Block RAM
FPGA AUX
and ADC, USB
Core
SRAM, USB
Controller,
PMOD, LEDS,
Buttons, FPGA
USER I/O
VCC1V0
VU
0.95V/1.00V/1.05V
1.2A
VCC1V8
VU
IC10
1.71V/1.80V/1.89V
0.6A
VCC3V3
VU
Switching
PS
IC10
3.135V/3.30V/3.465V
0.6A
Table 1.1. Power Rail Characteristics.
1.1
Power Input Options
It is possible to power the Cmod A7 from either USB or from an external power supply attached to pins 24 and 25
of the DIP connector, labeled “VU” and “GND”, respectively. The required characteristics of a power source
attached to either of these two options is outlined in Table 1.1.1.
Connector Type
USB
DIP
Connector Label
J3
J1 (Pin 24)
Schematic net name
USB5V0
VU
Table 1.1.1. Power source options.
Min/Rec/Max Voltage
4.5/5/5.5
3.32/5/5.5
The minimum external voltage that can be applied to VU depends on the amount of current drawn from the
VCC3V3 rail via the Pmod header. With 0mA drawn from the Pmod header, the minimum external voltage is 3.32V.
With 100mA drawn from the Pmod header, the minimum external voltage is 3.38V. With 250mA drawn from the
Pmod header, the minimum external voltage is 3.48V.
When the Cmod A7 is being powered by the USB connector, the voltage from the USB device is driven onto the VU
pin. This allows users to power an external circuit from the USB host in addition to the Cmod A7. The VU pin is
driven via a schottky diode, so a small voltage drop will occur, but it should be assumed the voltage present on VU
will be close to 5V.
Warning: When a USB host is attached to the Micro-USB connector, the VU pin on the DIP connector (pin 24) is
driven to the voltage being provided by the USB host (typically between 4.5V-5.5V). If you have a power source
attached to the VU pin, you must disconnect it before attaching a USB host, or risk damaging it. This can be
particularly dangerous if the power source is a battery.
Copyright Digilent, Inc. All rights reserved.
Other product and company names mentioned may be trademarks of their respective owners.
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2
FPGA Configuration
After power-on, the Artix-7 FPGA must be configured (or programmed) before it can perform any functions. Users
can configure the FPGA in one of two ways:
1.
2.
A PC can use the Digilent USB-JTAG circuitry to program the FPGA any time the power is on.
A file stored in the nonvolatile serial (Quad-SPI) flash device can be transferred to the FPGA using the SPI
port.
On power-up, the Cmod A7 is programmed by the Quad-SPI flash. If the FPGA does not find a valid configuration
file in the flash, then it will remain unconfigured until it is programmed over JTAG.
The FPGA configuration data is stored in files called bitstreams that have the .bit file extension. The Vivado
software from Xilinx can create bitstreams from VHDL or Verilog-based source files.
Bitstreams are stored in volatile memory cells within the FPGA. This data defines the FPGA’s logic functions and
circuit connections, and it remains valid until it is erased by removing board power, by pressing the reset button
attached to the PROG input, or by writing a new configuration file using the JTAG port.
Both the Artix-7 35T and 15T bitstreams are typically 17,536,096 bits. The time it takes to program the Cmod A7
can be decreased by compressing the bitstream before programming and then allowing the FPGA to decompress
the bitstream itself during configuration. Depending on design complexity, compression ratios of 10x can be
achieved. Bitstream compression can be enabled within the Vivado tools to occur during generation. For
instructions on how to do this, consult the Xilinx documentation for Vivado.
After being successfully programmed, the FPGA will cause the “DONE” LED to illuminate.
The following sections provide greater detail about programming the Cmod A7 using the different methods
available.
2.1
JTAG Configuration
The Xilinx tools typically communicate with FPGAs using the Test Access Port and Boundary-Scan Architecture,
commonly referred to as JTAG. During JTAG programming, a .bit file is transferred from the PC to the FPGA using
the onboard Digilent USB-JTAG circuitry (Micro-USB port). Users can perform JTAG programming any time after the
Cmod A7 has been powered on. If the FPGA is already configured, then the existing configuration is overwritten
with the bitstream being transmitted over JTAG.
Programming the Cmod A7 with an uncompressed bitstream using the on-board USB-JTAG circuitry usually takes
around 6 seconds. JTAG programming can be done using the hardware manager in Vivado.
Warning: When a USB host is attached to the Micro-USB connector, the VU pin on the DIP connector (pin 24) is
driven to the voltage being provided by the USB host (typically between 4.5V-5.5V). If you have a power source
attached to the VU pin, you must disconnect it before attaching a USB host, or risk damaging it. This can be
particularly dangerous if the power source is a battery.
2.2
Quad-SPI Configuration
Since the FPGA's memory on the Cmod A7 is volatile, it relies on the Quad-SPI flash memory to store the
configuration between power cycles. This configuration mode is referred to in Xilinx documentation as Master SPI.
The blank FPGA takes the role of master and reads the configuration file out of the flash device upon power-up. To
that effect, a configuration file needs to be downloaded first to the flash. When programming a nonvolatile flash
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device, a bitstream file is transferred to the flash in a two-step process. First, the FPGA is programmed with a
circuit that can program flash devices, and then data is transferred to the flash device via the FPGA circuit (this
complexity is hidden from the user by the Xilinx tools). This is called indirect programming. After the flash device
has been programmed, it can automatically configure the FPGA at a subsequent power-on event. Programming
files stored in the flash device will remain until they are overwritten, regardless of power-cycle events.
Programming the flash can take as long as four to five minutes, which is mostly due to the lengthy erase process
inherent to the memory technology. Once written, however, FPGA configuration can be very fast—less than a
second. Bitstream compression, SPI bus width, and configuration rate are factors controlled by the Xilinx tools that
can affect configuration speed. The Cmod A7 supports x1, x2, and x4 bus widths and data rates of up to 50 MHz for
Quad-SPI programming.
Quad-SPI programming can be done using the hardware manager in Vivado.
3
SRAM
The Cmod A7 includes 512 KB of Static Random-Access Memory (SRAM). This memory has a standard, easy-to-use
parallel interface with 19 address signals, 8 bi-directional data signals, and 3 control signals. The part used is the
ISSI IS61WV5128BLL-10BLI. The interface is fully documented in ISSI's
datasheet
for the part.
The power supply used to power the SRAM provides 3.3V with greater than 5% accuracy. This allows the
IS61WV5128BLL-10BLI part to be written to and read from with 8 ns access times. This allows for a theoretical
maximum data bandwidth of 125,000,000 B/s.
The onboard SRAM is very useful for MicroBlaze designs that would like to provide the processor with additional
memory. To do this, the SRAM can be controlled with Xilinx External Memory Controller IP core. The Cmod A7 User
demo available on the Cmod A7 resource center demonstrates how to do this.
For pin-mappings between the FPGA and SRAM, please see the CmodA7 Master XDC available on the Cmod A7
Resource Center.
4
Quad-SPI Flash
FPGA configuration files can be written to the Quad-SPI Flash (Micron part number N25Q032A) and the FPGA will
automatically configure itself with it after power on (as described in section 2.2). An Artix-7 35T or 15T
configuration file requires 17,536,096 bits of memory, leaving about half of the flash device (just over 2MB)
available for user data. A common use for this extra memory is to store MicroBlaze programs too big to fit in the
on-chip Block memory (typically 128 KB for the 35T and 64KB for the 15T). These programs are then loaded and
executed using a smaller bootloader program that can fit in the block memory. It is possible to automatically
generate this bootloader, roll it into a single file (called an .mcs file) that also contains the bitstream and your
custom MicroBlaze application, and program this file into SPI Flash using Xilinx SDK and Vivado. Xilinx Answer
Record 63605 explains how to do this.
The contents of the memory can be manipulated by issuing certain commands on the SPI bus. The implementation
of this protocol is outside the scope of this document. All signals in the SPI bus are general-purpose user I/O pins
after FPGA configuration. On other boards, SCK is an exception because it remains a dedicated pin even after
configuration, however, on the Cmod A7 the SCK signal is routed to an additional general purpose pin that can be
Copyright Digilent, Inc. All rights reserved.
Other product and company names mentioned may be trademarks of their respective owners.
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