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CPRI-E3-U4: 产品描述Development Software COMMON PUBLIC RADIO INTERFACE; 产品类别开发板/开发套件/开发工具; 文件大小2MB，共51页; 制造商Lattice(莱迪斯); 官网地址http://www.latticesemi.com; 标准

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CPRI-E3-U4概述

Development Software COMMON PUBLIC RADIO INTERFACE

CPRI-E3-U4规格参数

参数名称	属性值
Product Attribute	Attribute Value
制造商 Manufacturer	Lattice(莱迪斯)
产品种类 Product Category	Development Software
RoHS	Details
产品 Product	IP Core - CPRI
用于 For Use With	Lattice ECP3
Moisture Sensitive	Yes
工厂包装数量 Factory Pack Quantity	1

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CPRI IP Core

User Guide

FPGA-IPUG-02029 Version 2.8

July 2017

CPRI IP Core

User Guide

Contents

Introduction .................................................................................................................................................................. 4

1.1.

Quick Facts .......................................................................................................................................................... 5

1.2.

Features ............................................................................................................................................................... 6

2. Functional Description .................................................................................................................................................. 8

2.1.

Block Diagram...................................................................................................................................................... 8

2.2.

General Description............................................................................................................................................. 9

2.3.

Functional Overview.......................................................................................................................................... 12

2.4.

Signal Descriptions ............................................................................................................................................ 13

2.5.

Timing Specifications ......................................................................................................................................... 16

2.6.

CPRI Overview ................................................................................................................................................... 16

2.7.

Interfaces........................................................................................................................................................... 19

2.7.1. User Plane IQ Data Interface ........................................................................................................................19

2.7.2. Ethernet Interface ........................................................................................................................................21

2.7.3. HDLC Interface ..............................................................................................................................................23

2.7.4. L1 Inband Protocol Interface ........................................................................................................................24

2.7.5. Vendor Specific Information .........................................................................................................................24

2.7.6. Start-up Sequence ........................................................................................................................................25

3. Parameter Settings ..................................................................................................................................................... 26

3.1.

CPRI Configuration Dialog Box .......................................................................................................................... 26

3.1.1. Generation Options ......................................................................................................................................28

3.1.2. Eval Configuration ........................................................................................................................................28

3.2.

Programmable Parameters ............................................................................................................................... 28

4. IP Core Generation ..................................................................................................................................................... 29

4.1.

Licensing the IP Core ......................................................................................................................................... 29

4.2.

Getting Started .................................................................................................................................................. 29

4.3.

IPexpress-Created Files and Top Level Directory Structure .............................................................................. 32

4.4.

Instantiating the Core........................................................................................................................................ 35

4.5.

Running Functional Simulation ......................................................................................................................... 36

4.5.1. Using Aldec Active-HDL ................................................................................................................................36

4.5.2. Using Mentor Graphics ModelSim ...............................................................................................................36

4.6.

Synthesizing and Implementing the Core in a Top-Level Design ...................................................................... 37

4.7.

Hardware Evaluation ......................................................................................................................................... 37

4.7.1. Enabling Hardware Evaluation in Diamond ..................................................................................................37

4.8.

Updating/Regenerating the IP Core .................................................................................................................. 38

4.8.1. Regenerating an IP Core in IPexpress Tool ...................................................................................................38

4.8.2. Regenerating an IP Core in Clarity Designer Tool .........................................................................................38

5. Application Support .................................................................................................................................................... 40

5.1.

CPRI IP Top-Level Reference Design .................................................................................................................. 40

5.1.1. Test Bench ....................................................................................................................................................40

5.1.2. Register Descriptions ....................................................................................................................................41

References .......................................................................................................................................................................... 46

Technical Support Assistance ............................................................................................................................................. 46

Appendix A. Resource Utilization ....................................................................................................................................... 47

LatticeECP3-FPGAs ........................................................................................................................................................ 47

ECP5 FPGAs (for 3G Version) .......................................................................................................................................... 47

ECP5 FPGAs (for 5G Version) .......................................................................................................................................... 47

Revision History .................................................................................................................................................................. 48

www.latticesemi.com/legal.

All other brand or product names are

trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

FPGA-IPUG-02029-2.8

CPRI IP Core

User Guide

Figures

Figure 2.1. CPRI IP Logic Core Block Diagram ....................................................................................................................... 8

Figure 2.2. CPRI IP Core System Block Diagram in LatticeECP3 ............................................................................................ 9

Figure 2.3. CPRI IP Core System Block Diagram in ECP5 LFE5UM ....................................................................................... 10

Figure 2.4. Top-Level Template Included with CPRI IP Core ............................................................................................... 11

Figure 2.5. CPRI Protocol Overview .................................................................................................................................... 17

Figure 2.6. CPRI Frame (Shown for 614.4 Mbps, 1228.8 Mbps, 2457.6 Mbps, and 3072 Mbps Line Rates) ...................... 17

Figure 2.7. CPRI Frame (Shown for 614.4 Mbps, 1228.8 Mbps, 2457.6 Mbps, and 3072 Mbps Line Rates) ...................... 18

Figure 2.8. Tx User IQ Interface Sync Pulse Alignment ....................................................................................................... 19

Figure 2.9. Rx IQ Interface Data and Frame Number Alignment ........................................................................................ 20

Figure 2.10. Ethernet C&M Interface ................................................................................................................................. 21

Figure 2.11. Matched Rate MII CPRI Ethernet Interface .................................................................................................... 22

Figure 2.12. 100 Mbps Fixed Rate MII CPRI Ethernet Interface ......................................................................................... 23

Figure 2.13. HDLC C&M Interface ....................................................................................................................................... 23

Figure 2.14. Timing for Vendor-Specific Information Interface .......................................................................................... 25

Figure 3.1. CPRI Configuration Dialog Box .......................................................................................................................... 26

Figure 3.2. CPRI PCS Configuration Dialog Box ................................................................................................................... 26

Figure 3.3. CPRI PCS Advanced Configuration Dialog Box .................................................................................................. 27

Figure 4.1. IPexpress Dialog Box ......................................................................................................................................... 29

Figure 4.2. Clarity Designer Dialog Box ............................................................................................................................... 30

Figure 4.3. Configuration GUI ............................................................................................................................................. 30

Figure 4.4. PCS User Interface ............................................................................................................................................ 31

Figure 4.5. LatticeECP3 CPRI IP Core Directory Structure ................................................................................................... 32

Figure 4.6. LFE5UM CPRIIP Core Directory Structure ......................................................................................................... 32

Figure 4.7. Clarity Designer Builder Window ...................................................................................................................... 38

Figure 4.8. Clarity Designer Catalog Window ..................................................................................................................... 39

Figure 5.1. Pattern Generators and Checkers Included with Delivered IP Core Testbench (One Direction Shown) .......... 41

Tables

Table 1.1. CPRI IP Core Quick Facts (3G Version) ................................................................................................................. 5

Table 1.2. CPRI IP Core Quick Facts (5G Version) ................................................................................................................. 5

Table 2.1. CPRI I/O Signal Descriptions ............................................................................................................................... 13

Table 2.2. CPRI Line Rates ................................................................................................................................................... 18

Table 2.3. HDLC Frequencies Supported ............................................................................................................................ 24

Table 3.1. IP Core Parameters ............................................................................................................................................ 26

Table 3.2. CPRI Parameters Controlled via Input Signals to the IP Core ............................................................................. 28

Table 4.1. File List ............................................................................................................................................................... 33

Table 5.1. Supported Devices for Reference Design ........................................................................................................... 40

Table 5.2. CPRI Testbench Register Map ............................................................................................................................ 41

Table A.1. Resource Utilization ........................................................................................................................................... 47

Table A.2. Resource Utilization ........................................................................................................................................... 47

Table A.3. Resource Utilization ........................................................................................................................................... 47

www.latticesemi.com/legal.

All other brand or product names are

trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

FPGA-IPUG-02029-2.8

CPRI IP Core

User Guide

1. Introduction

This document provides technical information about the Lattice Semiconductor Common Public Radio Interface (CPRI)

IP core. This IP core together with SERDES and Physical Coding Sublayer (PCS) functionality integrated in the

LatticeECP3™ and ECP5™ LFE5UM FPGAs implements the physical layer of the CPRI specification and interleaves IQ

data with synchronization, control and management information. It can be used to connect Radio Equipment Control

(REC) and Radio Equipment (RE) modules.

The CPRI IP core implements all of the capabilities required to support the physical layer of the CPRI specification (basic

function), and also implements specific requirements related to link delay accuracy (low latency character). One CPRI

core configuration for 5G version (4.9152 Gbps) is also supported. This core configuration for 5G version is similar to

the "low latency" one for 3G version except the data rate. This document focuses on the detailed specifications

associated with implementing and using the basic function. The LatticeECP3 and ECP5 LFE5UM FPGAs optimize

PCS/SERDES architecture for low latency control. Complete details on the implementation and use of the low latency

configuration are included in

CPRI IP Core Low Latency Variation Design Considerations User’s Guide

(IPUG74).

The CPRI soft-core comes with the following documentation and files:



Data sheet



Protected netlist/database



Behavioral RTL simulation model



Source files for instantiating and evaluating the core

The CPRI IP core supports Lattice’s IP hardware evaluation capability, which makes it possible to create versions of the

IP core that operate in hardware for a limited period of time (approximately four hours) without requiring the purchase

of an IP license. It may also be used to evaluate the core in hardware in user-defined designs. The

Hardware Evaluation

section of this document details the hardware evaluation capability.

In this document, transmit refers to data flow from the user application logic to the CPRI link. Receive refers to data

flow from the CPRI link to the user application logic. Downlink refers to the direction of data flow from REC to RE, and

uplink refers to the direction of data flow from RE to REC.

The Lattice CPRI core is compliant with the version 5.0 CPRI specification. However, the core does not directly support

requirement R-31 (line-rate autonegotiation). For the 3G version, Lattice supports dynamic switching between full and

half rate line settings (i.e., 614M/1.2G or 1.2/2.4G). However, switching dynamically between all line rates is not

supported since some PCS/SERDES bit settings need to be re-programmed through the SCI to support reliable data

transfer. It is anticipated that in most network applications, line rate negotiation will be established/managed at the

system level and there is nothing in the IP core that precludes supporting such capability.

www.latticesemi.com/legal.

All other brand or product names are

trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

FPGA-IPUG-02029-2.8

CPRI-E3-U4相似产品对比

	CPRI-E3-U4	CPRI-PM-UT4	CPRI-E3-UT4
描述	Development Software COMMON PUBLIC RADIO INTERFACE	Development Software COMMON PUBLIC RADIO INTERFACE	Development Software COMMON PUBLIC RADIO INTERFACE
Product Attribute	Attribute Value	Attribute Value	Attribute Value
制造商 Manufacturer	Lattice(莱迪斯)	Lattice(莱迪斯)	Lattice(莱迪斯)
产品种类 Product Category	Development Software	Development Software	Development Software
RoHS	Details	Details	Details
产品 Product	IP Core - CPRI	IP Core - CPRI	IP Core - CPRI
用于 For Use With	Lattice ECP3	Lattice ECP2M	Lattice ECP3
Moisture Sensitive	Yes	Yes	Yes
工厂包装数量 Factory Pack Quantity	1	1	1

CPRI-E3-U4

CPRI-E3-U4在线购买

CPRI-E3-U4概述

CPRI-E3-U4规格参数

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CPRI-E3-U4相似产品对比

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