Si8920ISO-EVB
Si8920ISO-EVB U
SER
’
S
G
UIDE
Description
This document describes
Si8920ISO-EVB.
the
operation
of
the
Si8920ISO-EVB Overview
Kit Contents
The Si8920ISO Evaluation Kit contains the following
items:
Si8920ISO-EVB.
Si8920BC-IP installed on the evaluation board.
Rev. 0.1 8/15
Copyright © 2015 by Silicon Laboratories
Si8920ISO-EVB
Si8920ISO-EVB
1. Hardware Overview and Setup
1.1. Connecting to the EVB
Power the EVB by applying isolated 3.0 to 5.5 V
DC
supplies to terminal blocks J1 and J2. LEDs D21 and D22 will
light up. Use separate test points TP1, TP2, TP3, and TP4 for observing VDDA, GNDA, VDDB, and GNDB,
respectively.
Note:
DO NOT place jumpers across JP10, JP11, or JP12. These are redundant test points for VDDA, VDDB, and AOP/AON,
respectively.
There are three connection points for applying and observing differential signals to the inputs of Si8920:
1. Through a two conductor ribbon cable to 2x1 header JP8.
2. Clipping wires to test points TP7 and TP8.
3. Soldering wires directly to through holes located at TP9 and TP10.
The same connector options are available for observing and taking the output signals off circuit board:
1. Through a two conductor ribbon cable at 2x1 header JP12.
2. Clipping wires to test points TP5 and TP6.
3. Soldering wires directly through holes located at TP11 and TP12.
1.2. Driving Si8920 Inputs
Drive the inputs with a low impedance source. The Si8920 has a typical input impedance of 37.2 kΩ. A high source
impedance will affect the gain error of the amplifier. The maximum specified differential voltage is 200 mV and the
common mode must be within –250 mV to 1 V with respect to GNDA.
Note:
When driving inputs from a single-ended source, short the unused input to GNDA. If driving AIP input, install 0
Ω
resistor
across C23 pads. If driving AIN input, install a 0
Ω
resistor across C24 pads.
2
Rev. 0.1
Si8920ISO-EVB
1.3. Input Configuration
To measure input offset, install a jumper (not provided) at JP8 to short AIP and AIN together, and measure the
difference voltage between AOP and AON.
Si8920 has a channel bandwidth of approximately 750 kHz. R9-C7-R10 are populated providing low pass filtering
with cutoff frequency of approximately 400 kHz. If a different cutoff frequency is desired, replace C7 per Table 1. If
it is necessary to replace R9 and R10 for a specific cutoff frequency, ensure that R9 = R10 < 33
Ω.
Table 1. Input Filter Cutoff Frequency for Common Capacitor Values with R9 = R10 = 20
Ω
C7 (nF)
10*
15
22
33
47
*Note:
Installed value.
Cutoff Frequency (kHz)
398
265
181
121
85
Si8920 has excellent immunity to common mode transients. This EVB provides provisions for capacitors C23 and
C24 (not populated) between each input pin and GNDA. Placing a small capacitor at C23 and C24 can assist with
charge swapping between the inputs and GNDA during common mode transients. However, any mismatch
between C23 and C24 will result as a gain error at the output.
1.4. Observing Si8920 Outputs
Use a differential probe when observing the output using an oscilloscope. Most differential oscilloscope probes will
connect to the 2x1 headers JP12 without adapters. If only single-ended oscilloscope probes are available, use two
and set oscilloscope to subtract the two channels as one channel will only show half of the output.
Rev. 0.1
3
Si8920ISO-EVB
1.5. Output Configuration
By default, R23 and R24 are populated with 0
Ω
resistors that pass the output signal to the output connectors. If
low pass filtering at the output is required, replace R23 and R24 and populate C22.
R25 can be populated to measure the differential output drive strength. R26 and R27 can be populated to measure
the common mode drive strength to GNDB.
Table 2. Test Point Descriptions
Test Point
TP1
TP2
TP3
TP4
TP5
TP6
TP7
TP8
TP13
TP14
Description
VDDA
GNDA
VDDB
GNDB
AOP
AON
AIP
AIN
GNDA
GNDB
Reference
GNDA
N/A
GNDB
N/A
GNDB
GNDB
GNDA
GNDA
N/A
N/A
Table 3. Jumper Descriptions
Jumper
JP8
JP10
JP11
JP12
PIN 1
AIN
VDDA
VDDB
AON
PIN 2
AIP
GNDA
GNDB
AOP
Default Position
Not Installed
Not Installed
Not Installed
Not Installed
Description
Analog Input Connector, Short to Measure Offset
DO NOT SHORT
– test points only
DO NOT SHORT
– test points only
DO NOT SHORT
– test points only
4
Rev. 0.1
VDDB
VDDA
J1
R21
10K
R22
10K
J2
D23
5.6V
2
1
1
2
D22
RED
D20
5.6V
D21
RED
Input Side Power Supply
Valid ran ge: 3.3V to 5V +/
-
10%
Valid ran ge: 3.3V to 5V +/-10%
Output Side Power Supply
VDDA
TP13
GNDA
VDDA
VDDB
GNDA
TP2
TP1
TP3
TP4
TP14
GNDB
VDDB
GNDB
H1
JP10
JP11
VDDA
2. Si8920ISO-EVB Schematics
Do No t
Short
Do Not
Short
VDDB
TP7
AIP
AOP
TP6 TP12
AON
NI
NI
JP8
NI
AIP
AIN
AOP
AON
TP9
TP5 TP11
TP8 TP10
AIN
NI
Rev. 0.1
Input Connectors
GNDA
Si8920
JP12
Do Not
Short
Output Connectors
GNDB
Si8920ISO-EVB
Figure 1. Si8920ISO-EVB Schematic (1 of 2)
5
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