Critical Link, LLC
www.criticallink.com
MitySOM
MitySOM-1808 Processor Card
5-MAR-2014
FEATURES
TI AM1808 ARM9 Application Processor
-
456 MHz ARM926EJ-S MPU
16 KB L1 Program Cache
16 KB L1 Data Cache
8 KB Internal RAM
64 KB boot ROM
JTAG Emulation/Debug
(actual size)
APPLICATIONS
Industrial Automation
Industrial Instrumentation
Embedded Control Processing
Embedded User Interfaces
Test and Measurement
Medical Devices
BENEFITS
Rapid Development / Deployment
Multiple Connectivity and Interface Options
Rich User Interfaces
High System Integration
High Level OS Support
-
Linux
-
QNX 6.4
-
Windows Embedded CE Ready
-
ThreadX Real Time OS
Up To 256 MB mDDR2 CPU RAM
Up To 512 MB Parallel NAND FLASH
8 MB SPI based NOR FLASH
Integrated Power Management
Standard SO-DIMM-200 Interface
-
10/100 EMAC MII / RMII / MDIO
-
2 UARTS
-
2 McBSPs, 2 SPI, 2HPI
-
2 USB Ports
-
Video, LCD Output
-
Camera/Video Input
-
MMC/SD
-
SATA
-
ePWM, eCAP
-
EMIFA
-
Single 3.3V Power Supply
DESCRIPTION
The MitySOM-1808 is a highly configurable, very small form-factor processor card that
features a Texas Instruments AM1808 456 MHz ARM Applications Processor, FLASH
(NAND, and NOR) and mDDR2 RAM memory subsystems. The MitySOM-1808
provides a complete and flexible CPU infrastructure necessary for the most demanding
embedded applications development.
The AM1808 includes an ARM926EJ-S micro-processor unit (MPU) capable of running
the rich software applications programming interfaces (APIs) expected by modern system
designers. The ARM architecture supports several operating systems, including Linux,
QNX and Windows XP embedded. Linux drivers are available for all interfaces.
1
Copyright © 2013, Critical Link LLC
Specifications Subject to Change
Critical Link, LLC
www.criticallink.com
MitySOM
MitySOM-1808 Processor Card
5-MAR-2014
1.2V
1.8V
Up To 256MB
mDDR Memory
16-bit wide
8MB NOR Flash
(SPI interface)
For uBoot
bootloader
System
Clocks
JTAG
Header
JTAG/Emulator
Power
Management
3.3V
Texas Instruments
AM1808
456-MHz ARM926EJ-S ™ RISC MPU
(Many pins are multiplexed between peripherals)
EMAC MII/MDIO
Resets & RTC
EMAC RMII
UART 0,1,2
McBSP 0,1
MMCSD 0
MMCSD 1
eHRPWM
VPIF I/O
USB 0,1
McASP
SPI 0,1
I2C 0,1
Timers
eCAP
SATA
UHPI
LCD
uPP
Boot Config
EMIFA (16-bit)
Boot
Config
SO-DIMM-200 (DDR2 Connector)
Figure 1 MitySOM-1808 Block Diagram
Figure 1 provides a top level block diagram of the MitySOM-1808 processor card. As
shown in the figure, the primary interface to the MitySOM-1808 is through a standard
SO-DIMM-200 card edge interface. The interface provides power, synchronous serial
connectivity, and a rich set of interfaces available for application defined interfacing.
Details of the SO-DIMM-200 connector interface are included in the SO-DIMM-200
Interface Description, below.
AM1808 mDDR2 Memory Interface
The AM1808 includes a dedicated DDR2 SDRAM memory interface. The MitySOM-
1808 includes up to 256 MB of mDDR2 RAM integrated with the AM1808 processor.
The bus interface is capable of burst transfer rates of 600 MB / second. Note that the
OSCIN frequency to the AM1808 processor on the module is 24MHz.
AM1808 SPI NOR FLASH Interface
The MitySOM-1808 includes 8 MB of SPI NOR FLASH. This FLASH memory is
intended to store a factory provided bootloader, and typically a compressed image of a
Linux kernel for the ARM core processor.
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Copyright © 2013, Critical Link LLC
Specifications Subject to Change
3.3 V
GND
Up To 512MB
NAND Flash
8-bit wide
For root FFS
Critical Link, LLC
www.criticallink.com
MitySOM
MitySOM-1808 Processor Card
5-MAR-2014
EMIFA / NAND FLASH Interface
The Asynchronous External Memory Interface (EMIFA) interface available on the
AM1808 is available on the SO-DIMM-200 connector. The EMIFA interface includes 3
chip select spaces. The EMIF interface supports multiple data width transfers and bus
wait state configurations based on chip select space. 8, and 16 bit data word sizes may be
used.
Up to 512 MB of on-board NAND FLASH memory is connected to the AM1808 using
the EMIFA bus. The FLASH memory is 8 bits wide and is connected to the third chip
select line of the EMIFA (CE1). The FLASH memory is typically used to store the
following types of data:
-
ARM Linux / Windows Embedded CE / QNX embedded root file-system
-
runtime ARM software
-
runtime application data (non-volatile storage)
AM1808 Camera and Video Interfaces
The AM1808 includes an optional video port I/O interface commonly used to drive LCD
screens as well as a camera input interface. These interfaces have been routed directly to
the SO-DIMM-200 connector.
Debug Interface
The JTAG signals for the AM1808 processor have been brought out to a Hirose header
that is intended for use with an available Critical Link breakout adapter. This header can
be removed for production units; please contact your Critical Link representative for
details.
This adapter is not included with individual modules but is included with each Critical
Link Development Kit that is ordered. If an adapter, Critical Link (CL) part number 80-
000286, is needed please contact your Critical Link representative.
Software and Application Development Support
Users of the MitySOM-1808 are encouraged to develop applications using the MitySOM-
1808 software development kit provided by Critical Link LLC. The development kit
includes an implementation of an OpenEmbedded board support package providing an
Angstrom based Linux distribution and compatible gcc compiler tool-chain with
debugger.
Growth Options
The MitySOM-1808 has been designed to support several upgrade options. These options
include various speed grades, memory configurations, and operating temperature
specifications including commercial and industrial temperature ranges. The available
options are listed in the section below containing ordering information. For additional
ordering information and details regarding these options, or to inquire about a particular
configuration not listed below, please contact a Critical Link sales representative.
3
Copyright © 2013, Critical Link LLC
Specifications Subject to Change
Critical Link, LLC
www.criticallink.com
MitySOM
MitySOM-1808 Processor Card
5-MAR-2014
ABSOLUTE MAXIMUM RATINGS
If Military/Aerospace specified cards are
required, please contact the Critical Link Sales
Office or unit Distributors for availability and
specifications.
Maximum Supply Voltage, Vcc
3.5 V
OPERATING CONDITIONS
Ambient Temperature
Range Commercial
Ambient Temperature
Range Industrial
Humidity
MIL-STD-810F
0
o
C to 70
o
C
-40
o
C to 85
o
C
0 to 95%
Non-condensing
Contact Critical
Link for Details
Storage Temperature Range
Shock, Z-Axis
Shock, X/Y-Axis
-65 to 80C
±10 g
±10 g
SO-DIMM-200 Interface Description
The primary interface connector for the MitySOM-1808 is the SO-DIMM card edge
interface which contains 4 classes of signals:
Power (PWR)
Dedicated signals mapped to the AM1808 device (D)
Dedicated signals when NAND memory is populated on the module (D*)
Multi-function signals mapped to the AM1808 device (M)
Table 1 contains a summary of the MitySOM-1808 pin mapping.
Pin
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
Ball
-
-
-
-
-
K14
J1
J2
L1
L2
P16
P18
P19
N19
M18
M19
K18
-
-
-
Type
PWR
PWR
PWR
PWR
PWR
D
D
D
D
D
D
D
D
D
D
D
D
D
PWR
PWR
I/O
-
-
-
-
-
I
O
O
I
I
I
I/O
I/O
O
I/O
I/O
O
-
-
-
Table 1 SO-DIMM Pin-Out
Signal
Pin Ball
+3.3 V in
2
-
+3.3 V in
4
-
+3.3 V in
6
-
GND
8
-
GND
10
-
RESET_IN#
12
-
SATA_TX_P
14
A4
SATA_TX_N
16
A3
SATA_RX_P
18
A2
SATA_RX_N
20
A1
USB0_ID
22
B4
USB1_D_N
24
B1
USB1_D_P
26
B2
USB0_VBUS
28
B3
USB0_D_N
30
C2
USB0_D_P
32
C3
USB0_DRVVBUS
34
C4
3V RTC Battery
36
C5
+3.3 V in
38
-
+3.3 V in
40
-
Type
PWR
PWR
PWR
PWR
PWR
D
M
M
M
M
M
M
M
M
M
M
M
M
PWR
PWR
I/O
-
-
-
-
-
I
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
-
-
Signal
+3.3 V in
+3.3 V in
+3.3 V in
GND
GND
EXT_BOOT#
GP0_7
GP0_10
GP0_11
GP0_15
GP0_6
GP0_14
GP0_12
GP0_5
GP0_13
GP0_1
GP0_4
GP0_3
+3.3 V in
+3.3 V in
4
Copyright © 2013, Critical Link LLC
Specifications Subject to Change
Critical Link, LLC
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MitySOM
MitySOM-1808 Processor Card
5-MAR-2014
Signal
GND
SPI1_MISO
SPI1_MOSI
SPI1_ENA
SPI1_CLK
SPI1_SCS[1]
Reserved
I2C0_SCL
I2C0_SDA
UART2_TXD
I2C1_SDA
UART2_RXD
I2C1_SCL
GND
UART1_TXD
UART1_RXD
MDIO_CLK
MDIO_D
MII_RXCLK
MII_RXDV
MII_RXD[0]
MII_RXD[1]
MII_RXD[2]
MII_RXD[3]
GND
MII_CRS
MII_RXER
EMA_CS[0]
EMA_OE
EMA_BA[0]
EMA_BA[1]
EMA_A[0]
EMA_A[1]
EMA_A[2]
EMA_A[3]
GND
EMA_A[4]
EMA_A[5]
EMA_A[6]
EMA_A[7]
EMA_A[8]
EMA_A[9]
EMA_A[10]
Pin
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
Ball
-
D4
E4
F4
D5
A12
C11
E12
B11
E11
C10
-
A11
B10
A10
E9
D3
E3
E2
E1
F3
C1
-
D1
-
W15
V15
U18
V16
R14
W16
V17
W17
-
W18
W19
V18
V19
U16
U19
T16
Type
PWR
M
M
M
M
M
M
M
M
M
M
PWR
M
M
M
M
M
M
M
M
M
M
PWR
M
D
M
M
M
M
M
M
M
M
PWR
M
M
M
M
M
M
M
I/O
-
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
-
I/O
I/O
I/O
O
I
O
O
O
O
O
-
I
-
I/O
I
I/O
I/O
I/O
I/O
I/O
I/O
-
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Signal
GND
GP0_2
GP0_0
GP0_8
GP0_9
MMCSD0_DAT[7]
MMCSD0_DAT[6]
MMCSD0_DAT[5]
MMCSD0_DAT[4]
MMCSD0_DAT[3]
MMCSD0_DAT[2]
GND
MMCSD0_DAT[1]
MMCSD0_DAT[0]
MMCSD0_CMD
MMCSD0_CLK
MII_TXCLK
MII_TXD[3]
MII_TXD[2]
MII_TXD[1]
MII_TXD[0]
MII_TXEN
GND
MII_COL
NC
UPP_CHA_START
VP_CLKIN1
UPP_D[15]
/
RMII_TXD[1]
UPP_D[14]
/
RMII_TXD[0]
UPP_D[13]
/
RMII_TXEN
UPP_D[12]
/
RMII_RXD[1]
UPP_D[11]
/
RMII_RXD[0]
UPP_D[10]
/
RMII_RXER
GND
UPP_D[9]
/
RMII_REF_CLK
UPP_D[8]
/
RMII_CRS_DV
UPP_D[7]
UPP_D[6]
UPP_CHA_ENABLE
UPP_D[5]
UPP_D[4]
Pin
41
43
45
47
49
1
51
53
55
2
57
2
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
Ball
-
H17
G17
H16
G19
F18
-
G16
G18
F16
F17
-
F19
E18
E16
D17
D19
C17
D16
E17
D18
C19
-
C18
C16
A18
B15
C15
A15
C14
D15
B14
D14
-
A14
C13
E13
B13
A13
D12
C12
Type
PWR
D
D
D
D
M
D
D
D
M
M
PWR
M
M
M
M
M
M
M
M
M
M
PWR
M
M
M
D*
M
M
M
D*
D*
M
PWR
M
M
M
M
M
M
M
I/O
-
I/O
I/O
I/O
I/O
I/O
-
I/O
I/O
I/O
I/O
-
O
I
O
I/O
I
I
I
I
I
I
-
I
I
O
O
O
O
O
O
O
O
-
O
O
O
O
O
O
O
/
/
5
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Specifications Subject to Change
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