DATA SHEET
MOS INTEGRATED CIRCUIT
µ
PD720130
USB2.0 to IDE Bridge
The
µ
PD720130 is designed to perform a bridge between USB 2.0 and ATA/ATAPI. The
µ
PD720130 complies
with the Universal Serial Bus Specification Revision 2.0 full-/high-speed signaling and works up to 480 Mbps. The
µ
PD720130 is integrated CISC processor, ATA/ATAPI controller, endpoint controller (EPC), serial interface engine
(SIE), and USB2.0 transceiver into a single chip.
The USB2.0 protocol and class specific protocol (bulk only
protocol) are handled by USB2.0 transceiver, SIE, and EPC. And the transport layer is performed by V30MZ CISC
processor which is in the
µ
PD720130. The software to control the
µ
PD720130 is located in an embedded ROM. In
the future, the
µ
PD720130 will be released to support external Flash Memory / EEPROM™ option to update function
by firmware.
Detailed function descriptions are provided in the following user’s manual. Be sure to read the manual before designing.
µ
PD720130 User’s Manual: S16412E
FEATURES
• Compliant with Universal Serial Bus Specification Revision 2.0 (Data Rate 12/480 Mbps)
• Compliant with ATA/ATAPI-6 (LBA48, PIO Mode 0-4, Multi Word DMA Mode 0-2, Ultra DMA Mode 0-4)
• USB2.0 high-speed bus powered device capability
• Certified by USB implementers forum and granted with USB 2.0 high-speed Logo (TID :40320125)
• One USB2.0 high-speed transceiver / receiver with full-speed transceiver / receiver
• USB2.0 High-speed or Full-speed packet protocol sequencer (Serial Interface Engine)
• Automatic chirp assertion and full-/high-speed mode change
• USB Reset, Suspend and Resume signaling detection
• Supports power control functionality for IDE device as CD-ROM and HDD
• Supports set feature (TEST_MODE) functionality
• System Clock is generated by 30 MHz X’tal
• 2.5 V and 3.3 V power supply
ORDERING INFORMATION
Part Number
Package
100-pin plastic TQFP (fine pitch) (14
×
14)
100-pin plastic TQFP (fine pitch) (14
×
14)
µ
PD720130GC-9EU
µ
PD720130GC-9EU-SIN
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No. S16302EJ3V0DS00 (3rd edition)
Date Published June 2003 NS CP (K)
Printed in Japan
The mark
shows major revised points.
2002
µ
PD720130
BLOCK DIAGRAM
CPU Core
(V30MZ)
RAM
4 Kbytes×2
ROM
8 Kbytes
EPC2_V2
PHY_V2
USB Bus
DCC
16-bit Bus
Bus Bridge
16-bit Bus
IDEC_V2
IDE Bus
DMAC
GPIO
GPIO
or
FSIO
FSIO
PIO
INTC
8-bit Bus
Timer
Direct Bus
Direct Command Bus
Ext. Bus (Data 8-bit Bus) or PIO
Serial
ROM
V30MZ
RAM
ROM
PHY_V2
EPC_V2
IDEC_V2
DCC
Bus Bridge
INTC
GPIO
PIO
FSIO
: CISC CPU core
: 8-Kbyte work RAM for firmware
: 8-Kbyte ROM for built-in firmware
: USB2.0 transceiver with serial interface engine
: Endpoint controller
: IDE controller
: ATA direct command controller
: Internal / external bus controller and DMA controller
: Interrupt controller (82C59 like)
: General purpose 8-bit I/O controller
: Multipurpose 14-bit I/O controller
: Flexible serial I/O
2
Data Sheet S16302EJ3V0DS
µ
PD720130
1.
PIN INFORMATION
(1/2)
Pin Name
I/O
Buffer Type
Active
Level
Function
XIN
XOUT
RESETB
MD(1:0)
IDECS(1:0)B
IDEA(2:0)
IDEINT
IDEDAKB
IDEIORDY
IDEIORB
IDEIOWB
IDEDRQ
IDED(15:0)
IDERSTB
DCC
DV(1:0)
CLC
PWR
CMB_BSY
CMB_STATE
DPC
SDA
SCL
VBUS
DP
DM
RSDP
RSDM
RPU
RREF
SPD
SMC
TEST(3:0)
I
O
I
I
O (I/O)
O (I/O)
I (I/O)
O (I/O)
I (I/O)
O (I/O)
O (I/O)
I (I/O)
I/O
O (I/O)
I (I/O)
I (I/O)
I (I/O)
I (I/O)
O (I/O)
I (I/O)
O (I/O)
I/O
I/O
I
I/O
I/O
O
O
A
A
I (I/O)
I
I
2.5 V Input
2.5 V Output
3.3 V Schmitt Input
3.3 V Input
5 V tolerant Output
5 V tolerant Output
5 V tolerant Input
5 V tolerant Output
5 V tolerant Input
5 V tolerant Output
5 V tolerant Output
5 V tolerant Input
5 V tolerant I/O
5 V tolerant Output
3.3 V Input
3.3 V Input
3.3 V Input
3.3 V Input
3.3 V Output
3.3 V Input
3.3 V Output
3.3 V I/O
3.3 V I/O
5 V Schmitt Input
Note
USB high speed D+ I/O
USB high speed D− I/O
USB full speed D+ Output
USB full speed D− Output
USB Pull-up control
Analog
3.3 V Input
3.3 V Input
3.3 V Input
Low
High
Low
High
Low
Low
High
Low
Low
System clock input or oscillator In
Oscillator out
Asynchronous reset signaling
Function mode setting
IDE host chip select
IDE address bus
IDE interrupt request from device to host
IDE DMA acknowledge
IDE IO channel ready
IDE IO read strobe
IDE IO write strobe
IDE DMA request from device to host
IDE data bus
IDE reset from host to device
IDE controller operational mode setting
Device select
System clock setting
Bus powered /self-powered select
Combo IDE bus busy
Combo IDE bus state
Power control signaling for IDE device
Serial ROM data signaling
Serial ROM clock signaling
VBUS monitoring
USB’s high speed D+ signal
USB’s high speed D− signal
USB’s full speed D+ signal
USB’s full speed D− signal
USB’s 1.5 kΩ pull-up resistor control
Reference resistor
NEC private
Scan mode control
Test mode setting
Note
VBUS pin may be used to monitor for VBUS line even if V
DD33
, V
DD25
, and AV
DD25
are shut off. System must
ensure that the input voltage level for VBUS pin is less than 3.0 V due to the absolute maximum rating is
not exceeded.
Data Sheet S16302EJ3V0DS
5
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