LAN91C111
10/100 Non-PCI
Ethernet Single Chip
MAC + PHY
PRODUCT FEATURES
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Datasheet
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Single Chip Ethernet Controller
Dual Speed - 10/100 Mbps
Fully Supports Full Duplex Switched Ethernet
Supports Burst Data Transfer
8 Kbytes Internal Memory for Receive and Transmit
FIFO Buffers
Enhanced Power Management Features
Optional Configuration via Serial EEPROM Interface
Supports 8, 16 and 32 Bit CPU Accesses
Internal 32 Bit Wide Data Path (Into Packet Buffer
Memory)
Early TX, Early RX Functions
Built-in Transparent Arbitration for Slave Sequential
Access Architecture
Flat MMU Architecture with Symmetric Transmit and
Receive Structures and Queues
3.3V Operation with 5V Tolerant IO Buffers (See Pin
List Description for Additional Details)
Single 25 MHz Reference Clock for Both PHY and
MAC
External 25Mhz-output pin for an external PHY
supporting PHYs physical media.
Low Power CMOS Design
Supports Multiple Embedded Processor Host
Interfaces
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ARM
SH
Power PC
Coldfire
680X0, 683XX
MIPS R3000
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3.3V MII (Media Independent Interface) MAC-PHY
Interface Running at Nibble Rate
MII Management Serial Interface
128 Pin QFP package; green, lead-free package also
available.
128 Pin TQFP package, 1.0 mm height; green, lead-
free package also available.
Industrial Temperature Range from -40°C to 85°C
(LAN91C111i only)
Network Interface
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Fully Integrated IEEE 802.3/802.3u-100Base-TX/
10Base-T Physical Layer
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Auto Negotiation: 10/100, Full / Half Duplex
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On Chip Wave Shaping - No External Filters
Required
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Adaptive Equalizer
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Baseline Wander Correction
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LED Outputs (User selectable – Up to 2 LED
functions at one time)
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Link
Activity
Full Duplex
10/100
Transmit
Receive
SMSC LAN91C111-REV B
DATASHEET
Revision 1.8 (07-13-05)
10/100 Non-PCI Ethernet Single Chip MAC + PHY
Datasheet
ORDER NUMBER(S):
LAN91C111-NC, LAN91C111i-NC (INDUSTRIAL TEMPERATURE)
FOR 128 PIN QFP PACKAGES
LAN91C111-NS, LAN91C111i-NS (INDUSTRIAL TEMPERATURE)
FOR 128 PIN QFP PACKAGES (GREEN, LEAD-FREE)
LAN91C111-NE (1.0MM HEIGHT); LAN91C111i-NE (INDUSTRIAL TEMPERATURE)
FOR 128 PIN TQFP PACKAGES
LAN91C111-NU (1.0MM HEIGHT); LAN91C111i-NU (INDUSTRIAL TEMPERATURE)
FOR 128 PIN TQFP PACKAGES (GREEN, LEAD-FREE)
80 Arkay Drive
Hauppauge, NY 11788
(631) 435-6000
FAX (631) 273-3123
Copyright © 2005 SMSC or its subsidiaries. All rights reserved.
Circuit diagrams and other information relating to SMSC products are included as a means of illustrating typical applications. Consequently,
complete information sufficient for construction purposes is not necessarily given. Although the information has been checked and is believed to be
accurate, no responsibility is assumed for inaccuracies. SMSC reserves the right to make changes to specifications and product descriptions at any
time without notice. Contact your local SMSC sales office to obtain the latest specifications before placing your product order. The provision of this
information does not convey to the purchaser of the described semiconductor devices any licenses under any patent rights or other intellectual
property rights of SMSC or others. All sales are expressly conditional on your agreement to the terms and conditions of the most recently dated
version of SMSC's standard Terms of Sale Agreement dated before the date of your order (the "Terms of Sale Agreement"). The product may
contain design defects or errors known as anomalies which may cause the product's functions to deviate from published specifications. Anomaly
sheets are available upon request. SMSC products are not designed, intended, authorized or warranted for use in any life support or other
application where product failure could cause or contribute to personal injury or severe property damage. Any and all such uses without prior written
approval of an Officer of SMSC and further testing and/or modification will be fully at the risk of the customer. Copies of this document or other
SMSC literature, as well as the Terms of Sale Agreement, may be obtained by visiting SMSC’s website at http://www.smsc.com. SMSC is a
registered trademark of Standard Microsystems Corporation (“SMSC”). Product names and company names are the trademarks of their respective
holders.
SMSC DISCLAIMS AND EXCLUDES ANY AND ALL WARRANTIES, INCLUDING WITHOUT LIMITATION ANY AND ALL IMPLIED
WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, TITLE, AND AGAINST INFRINGEMENT AND THE LIKE,
AND ANY AND ALL WARRANTIES ARISING FROM ANY COURSE OF DEALING OR USAGE OF TRADE.
IN NO EVENT SHALL SMSC BE LIABLE FOR ANY DIRECT, INCIDENTAL, INDIRECT, SPECIAL, PUNITIVE, OR CONSEQUENTIAL
DAMAGES; OR FOR LOST DATA, PROFITS, SAVINGS OR REVENUES OF ANY KIND; REGARDLESS OF THE FORM OF ACTION,
WHETHER BASED ON CONTRACT; TORT; NEGLIGENCE OF SMSC OR OTHERS; STRICT LIABILITY; BREACH OF WARRANTY; OR
OTHERWISE; WHETHER OR NOT ANY REMEDY OF BUYER IS HELD TO HAVE FAILED OF ITS ESSENTIAL PURPOSE, AND WHETHER
OR NOT SMSC HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
Revision 1.8 (07-13-05)
DATASHEET
2
SMSC LAN91C111-REV B
10/100 Non-PCI Ethernet Single Chip MAC + PHY
Datasheet
0.1
Datasheet Revision History
Table 0.1 LAN91C111 Datasheet Revision History
REVISION
LEVEL AND
DATE
Rev. 1.8
(07-13-05)
NAME
K. Lawrence
SECTION/FIGURE/ENTRY
Chapter 14, "Timing
Diagrams," on page 125
-
(Figure
14.1, Figure 14.2,
and
Figure 14.3),
and
Chapter 8,
MAC Data Structures and
Registers
Ordering Information
Chapter 14, "Timing
Diagrams," on page 125
-
(Figure
14.1, Figure 14.2,
and
Figure 14.3)
Table 10.2, “Flow Of Events
For Restoring Device In
Normal Power Mode,” on
page 96
Section 7.7.17, "PHY
Powerdown," on page 50
Chapter 5, "Description of Pin
Functions," on page 23
Table 9.2, “MII Serial Port
Register MAP,” on page 84
Features
Section 13.1, "Maximum
Guaranteed Ratings*," on
page 119
Section 8.2, "Receive Frame
Status," on page 54
Section 8.5, "Bank 0 -
Transmit Control Register," on
page 57
Section 8.6, "Bank 0 - EPH
Status Register," on page 58
Section 8.12, "Bank 1 - Base
Address Register," on
page 65
Chapter 5, "Description of Pin
Functions," on page 23
Section 7.7.12, "Link Integrity
& Autonegotiation," on
page 46
Section 7.8, "Reset," on
page 51
3
CORRECTION
Fixed t4 MIN/MAX values. Clarified CRC
in RX packet description.
Rev. 1.7
(11-16-04)
Rev. 1.6
(05-18-04)
Lead-free added.
Modified t1 and t4.
Rev. 1.6
(05-18-04)
Modified description of restoring to normal
power mode.
Rev. 1.6
(05-18-04)
Rev. 1.5
(02-20-04)
Rev. 1.5
(02-20-04)
Rev. 1.4
(12-12-03)
Rev. 1.3
(07-29-03)
Rev. 1.3
(07-18-03)
Rev. 1.3
(07-18-03)
Rev. 1.3
(07-18-03)
Rev. 1.2
(09-17-02)
Rev. 1.0
(07-01-02)
Rev. 1.0
(07-01-02)
Rev. 1.0
(07-01-02)
SMSC LAN91C111-REV B
Modified description of PHY power down
mode.
Modified description of INTR0 pin active
high.
Modified Reg.18 LNKFAIL bit to “0” by
default.
Removed “user programmable” under
LED Output features.
Modified LAN91C111 Temp 0°C to +85°C.
Modified description of the BROADCAST
bit in Receive Frame Status.
Modified description of the STP_SQET bit
in TCR Register.
Modified description of SQET bit in EPH
Status Register.
Added chart showing decoding of I/O
Base Address 300h.
Add Buffer Type for nLEDA and nLEDB,
Add description of LCLK.
Modified Auto-Negotiation Enable
Description.
Add Reset Description.
DATASHEET
Revision 1.8 (07-13-05)
10/100 Non-PCI Ethernet Single Chip MAC + PHY
Datasheet
Table 0.1 LAN91C111 Datasheet Revision History (continued)
REVISION
LEVEL AND
DATE
Rev. 1.0
(07-01-02)
Rev. 1.0
(07-01-02)
Rev. 1.0
(07-01-02)
Rev. 1.0
(07-01-02)
Rev. 1.0
(07-01-02)
Rev. 1.0
(07-01-02)
Rev. 1.0
(07-01-02)
Rev. 1.0
(07-01-02)
NAME
SECTION/FIGURE/ENTRY
Section 8.5, "Bank 0 -
Transmit Control Register," on
page 57
Section 8.10, "Bank 0 -
Receive/Phy Control
Register," on page 61
Section 8.21, "Bank 2 -
Interrupt Status Registers," on
page 72
Figure 8.2 Interrupt
Structureon page 75
Chapter 9, "PHY MII
Registers ," on page 81
Section 9.10, "Register 20.
Reserved - Structure and Bit
Definition," on page 93
Section 10.2, "Typical Flow of
Events for Transmit (Auto
Release = 0)," on page 96
Section 10.3, "Typical Flow of
Events for Transmit (Auto
Release = 1)," on page 97
CORRECTION
Add Description for FDUPLX bit.
Add Description for SPEED, DPLX, ANEG
bits.
Add Description for Interrupt Status and
Mask bits.
Modified Interrupt Structure Figure.
Changed bit name 0 to Reserved.
Reserved bits default at 00A0.
Modified Typical Flow of Event for TX.
Modified Typical Flow of Event for TX.
SMSC LAN91C111-REV B
DATASHEET
4
Revision 1.8 (07-13-05)
10/100 Non-PCI Ethernet Single Chip MAC + PHY
Datasheet
Table of Contents
0.1
Datasheet Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Chapter 1 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Chapter 2 Pin Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Chapter 3 Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Chapter 4 Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Chapter 5 Description of Pin Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Chapter 6 Signal Description Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
6.1
Buffer Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Chapter 7 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
7.1
7.2
7.3
7.4
7.5
Clock Generator Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CSMA/CD Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.2.1
DMA Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.2.2
Arbiter Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MMU Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
BIU Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MAC-PHY Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.5.1
Management Data Software Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.5.2
Management Data Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.5.3
MI Serial Port Frame Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.5.4
MII Packet Data Communication with External PHY . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Serial EEPROM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Internal Physical Layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.7.1
MII Disable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.7.2
Encoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.7.3
Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.7.4
Clock and Data Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.7.5
Scrambler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.7.6
Descrambler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.7.7
Twisted Pair Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.7.8
Twisted Pair Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.7.9
Collision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.7.10 Start of Packet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.7.11 End of Packet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.7.12 Link Integrity & Autonegotiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.7.13 Jabber . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.7.14 Receive Polarity Correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.7.15 Full Duplex Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.7.16 Loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.7.17 PHY Powerdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.7.18 PHY Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
29
29
29
29
29
30
30
30
31
31
33
34
34
36
36
36
38
38
38
39
42
44
44
45
46
49
49
50
50
50
50
51
7.6
7.7
7.8
Chapter 8 MAC Data Structures and Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
8.1
8.2
Frame Format In Buffer Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Receive Frame Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
SMSC LAN91C111-REV B
DATASHEET
5
Revision 1.8 (07-13-05)
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