LF3321
Horizontal Digital Image Filter
DEVICES INCORPORATED
Improved Performance
FEATURES
111 MHz Data Rate
12-bit Data or Coefficients (Expandable to 24-bit)
32-Tap FIR Filter, Cascadable for More Filter Taps
LF Interface™ Allows All 256 Coefficient Sets to be
Updated Within Vertical Blanking
Over 49 K-bits of on-board Memory
Various Operating Modes: Dual Filter, Single Filter,
Double Wide Data or Coefficient, Matrix Multiplica-
tion, and Accumulator Access.
Selectable 16-bit Data Output with User-Defined
Rounding and Limiting
Supports Interleaved Data Streams
Supports Decimation up to 16:1 for Increas-
ing Number of Filter Taps
3.3 Volt Power Supply
144 Lead PQFP
DESCRIPTION
The LF3321 is an improved version of the LF3320 Horizontal Digital Image Filter capable of operating at
speeds of up to 111MHz. This improved speed increases flexibility and performance and enables the user
to utilize this device in more applications. For example, four interleaved data streams of 27MHz can now
be processed within one device. The part is functionally identical to the LF3320 with the exception that the
filter data path is specified to operate faster than the LF Control Interface. When operating the filter at
speeds in excess of 90MHz, loading of coefficients via the LF Interface must be throttled to a maximum
of 90MHz by asserting the PAUSE pin as required to allow sufficient setup time for the configuration data
provided to the chip via the LF Interface.
Figure 1. Switching Waveforms: LF Interface
TM
CLK
tS0
LDA
LDB
PAUSEA
PAUSEB
CFA 11-0
CFB 11-0
tCFH
tCFS
ADDRESS
CF0
CF1
tPS
tPWH
tPWL
tLH
tCYC
tPH
Figure 1 demonstrates the switching waveforms, while the switching characteristics are given in Table
1. The LF3321 filters digital images in the horizontal dimension at real-time video rates. The input and
coefficient data are both 12 bits and in two’s complement format. The output is also in two’s complement
format and may be rounded to 16 bits.
The LF3321 is designed to take advantage of symmetric coefficient sets. When symmetric coefficient sets
are used, the device can be configured as a single 32-tap FIR filter or as two separate 16-tap FIR filters.
When asymmetric coefficient sets are used, the device can be configured as a single 16-tap FIR filter or as
two separate 8-tap FIR filters. Multiple LF3321s can be cascaded to create larger filters.
Interleave/Decimation Registers (I/D Registers) allow interleaved data to be fed directly into the device and
filtered without separating the data into individual data streams.
The LF3321 can handle a maximum of sixteen data sets interleaved together. The I/D Registers and
on-chip accumulators facilitate using decimation to increase the number of filter taps. Decimation of up
to 16:1 is supported.
The LF3321 contains enough on-board memory to store 256 coefficient sets. Two separate LF Interfaces
TM
allow all 256 coefficient sets to be updated within vertical blanking.
LOGIC Devices Incorporated
1
Video Imaging Products
Feb 5, 2003 LDS.3321-A
LF3321
Horizontal Digital Image Filter
DEVICES INCORPORATED
Improved Performance
DESCRIPTION
Table 1. Switching Characteristics
Commercial Operating Range (0ºC to + 70ºC)
9
*
(ns) speed grade
Symbol
t
CYC
t
PWL
t
PWH
t
S0
t
H0
t
SCT
t
HCT
t
SCC
t
HCC
t
D
t
DCC
t
DIS
t
DIS
Parameter
Cycle Time
Clock Pulse Width Low
Clock Pulse Width High
Input Setup Time
Input Hold Time
Setup Time Control Inputs
Hold Time Control Inputs
Setup Time Coefficient Control Inputs
Hold Time Coefficient Control Inputs
Output Delay
Cascade Output Delay
Three State Output Display Delay
Three State Output Enable Delay
MIN
9
4
4
4
0
4
0
4
0
MAX
8
7.5
10
10
Figure 2. LF3321 Block Diagram
ROUT
11-0
12
12
RIN
11-0
DIN
11-0
CAA
7-0
CENA
CFA
11-0
PAUSEA
LDA
12
INTERLEAVE / DECIMATION
REGISTERS
12
COUT
11-0
CAB
7-0
CENB
8
8
12
256
COEFFICIENT
SET
STORAGE
16-TAP
FILTER A
16-TAP
FILTER B
256
COEFFICIENT
SET
STORAGE
12
CFB
11-0
PAUSEB
LDB
ROUND
SELECT
LIMIT
CIRCUITRY
CLK
OED
16
DOUT
15-0
LOGIC Devices Incorporated
2
Video Imaging Products
Feb 5, 2003 LDS.3321-A
DEVICES INCORPORATED
1-16
1-16
1-16
1-16
1-16
1-16
1-16
1-16
1-16
1-16
1-16
1-16
1-16
1-16
1-16
1-16
CENA
RSLB
OUT
11-0
LDA
CFA
11-0
PAUSEA
CFB
11-0
ACCA
32
32
SCALE
32
"0"
PAUSEB
ACCM A
ACCM B
LDB
LOGIC Devices Incorporated
FILTER B I/D REGISTERS
12
RIN
11-0
OEC
ROUT
3-0
4
RSLB OUT
15-12
FILTER A I/D REGISTERS
R E O I
S E O I
DATA
REVERSAL
DATA
REVERSAL
1-16
1-16
1-16
1-16
1-16
1-16
1-16
1-16
1-16
1-16
1-16
1-16
1-16
1-16
ROUT
11-4
8
DIN
11-0
12
COUT
11-0
A
ALU
CAB
7-0
8
CENB
Coef Bank 15
B
12
OEC
A
ALU
ALU
ALU
ALU
ALU
ALU
ALU
ALU
ALU
ALU
B
A
A
A
A
A
A
A
A
A
B
B
B
B
B
B
B
B
B
DESCRIPTION
CAA
7-0
ALU
B
A
ALU
B
A
ALU
B
A
ALU
B
A
ALU
B
A
8
13
12
13
13
13
13
13
13
13
13
13
13
13
13
13
13
13
Coef Bank 0
12
Coef Bank 14
12
Coef Bank 1
12
Coef Bank 13
12
Coef Bank 2
12
12
Coef Bank 3
12
12
Coef Bank 12
Figure 3. LF3321 Functional Block Diagram
3
12
12
12
25
25
25
25
25
25
25
25
25
25
27
27
CONFIGURATION AND
CONTROL REGISTERS
27
32
ROUND
SELECT
LIMIT
ROUND
SELECT
LIMIT
Coef Bank 4
12
Coef Bank 11
Coef Bank 5
12
Coef Bank 10
Coef Bank 6
12
Coef Bank 9
Coef Bank 7
12
Coef Bank 8
25
25
25
25
25
25
FILTER A
LF
INTERFACE
27
FILTER B
LF
INTERFACE
12
12
ACCB
"0"
TXFRA
TXFRB
RSLA
3-0
FILTER A
16
4
4
FILTER B
16
RSLB OUT
15-0
RSLB
3-0
SHENA
SHENB
16
DOUT
15-0
OED
LF3321
Horizontal Digital Image Filter
Improved Performance
Video Imaging Products
Feb 5, 2003 LDS.3321-A
CLK
LF3321
Horizontal Digital Image Filter
DEVICES INCORPORATED
Improved Performance
Functional Description
ALU
The ALUs double the number of filter taps available, when symmetric coefficient sets are used, by pre-
adding data values which are then multiplied by a common coefficient (see Figure 4). The ALUs can
perform two operations: A+B and B–A. Bit 0 of Configuration Register 0 determines the operation of the
ALUs in Filter A. Bit 0 of Configuration Register 2 determines the operation of the ALUs in Filter B. A+B is
used with even-symmetric coefficient sets. B–A is used with odd-symmetric coefficient sets.
Also, either the A or B operand may be set to 0. Bits 1 and 2 of Configuration Register 0 and Configuration
Register 2 control the ALU inputs in Filters A and B respectively. A+0 or B+0 are used with asymmetric
coefficient sets.
Figure 4. Symmetric Coefficient Set Examples
8 7 6 5
8 7 6 5 4 3 2 1
Even-Tap, Even-Symmetric
Coefficient Set
7 6 5 4 3 2 1
Odd-Tap, Even-Symmetric
Coefficient Set
4 3 2 1
Even-Tap, Odd-Symmetric
Coefficient Set
I/D Registers
The Interleave/Decimation Registers (I/D Registers), feed the ALU inputs. They allow the device to filter up
to sixteen data sets interleaved into the same data stream without having to separate the data sets. The I/D
Registers should be set to a length equal to the number of data sets interleaved together.
For example, if two data sets are interleaved together, the I/D Registers should be set to a length of two.
Bits 1 through 4 of Configuration Register 1 and Configuration Register 3 determine the length of the I/D
Registers in Filters A and B respectively.
The I/D Registers also facilitate using decimation to increase the number of filter taps. Decimation by N is
accomplished by reading the filter’s output once every N clock cycles. The device supports decimation up to
16:1. With no decimation, the maximum number of filter taps is sixteen. When decimating by N, the number
of filter taps becomes 16N because there are N–1 clock cycles when the filter’s output is not being read. The
extra clock cycles are used to calculate more filter taps.
When decimating, the I/D Registers should be set to a length equal to the decimation factor. For example,
when performing a 4:1 decimation, the I/D Registers should be set to a length of four. When decimation is
disabled or when only one data set (non-interleaved data) is fed into the device, the I/D Registers should
be set to a length of one.
I/D Registers Data
Path Control
The three multiplexers in the I/D Register data path control how data is routed through the forward and
reverse data paths. The forward data path contains the I/D Registers in which data flows from left to right
in the block diagram in Figure 1. The reverse data path contains the I/D Registers in which data flows from
right to left. In Single or Dual Filter Modes, data is fed from the forward data path to the reverse data path
as follows. When the filter is configured for an even number of taps, data from the last I/D Register in the
forward data path is fed into the first I/D Register in the reverse data path (see Figure 5). When the filter
is configured for an odd number of taps, the data which will appear at the output of the last I/D Register
in the forward data path on the next clock cycle is fed into the first I/D Register in the reverse data path.
Bit 5 in Configuration Register 1 and Configuration Register 3 configures Filters A and B respectively for
an even or odd number of taps.
LOGIC Devices Incorporated
4
Video Imaging Products
Feb 5, 2003 LDS.3321-A
LF3321
Horizontal Digital Image Filter
DEVICES INCORPORATED
Improved Performance
Functional Description
Figure 5. I/D Register Data Paths
DATA
REVERSAL
DATA
REVERSAL
DATA
REVERSAL
1-16
1-16
1-16
1-16
1-16
1-16
1-16
1-16
1-16
1-16
1-16
Delay Stage N
A
ALU
B
A
ALU
B
A
ALU
B
A
ALU
B
A
ALU
B
1-16
Delay Stage N 1
A
ALU
B
COEF 7
COEF 6
COEF 7
2
COEF 6
COEF 7
2
COEF 6
EVEN-TAP MODE
ODD-TAP MODE
ODD-TAP INTERLEAVE MODE
When interleaved data is fed through the device and an even tap filter is desired, the filter should be
configured for an even number of taps and the I/D Register length should match the number of data sets
interleaved together. When interleaved data is fed through the device and an odd tap filter is desired, the
filter should be set to Odd-Tap Interleave Mode. Bit 0 of Configuration Register 1 and Configuration Register
3 configures Filters A and B respectively for Odd-Tap Interleave Mode. When the filter is configured for
Odd-Tap Interleave Mode, data from the next to last I/D Register in the forward data path is fed into the
first I/D Register in the reverse data path.
When the filter is configured for an odd number of taps (interleaved or non-interleaved modes), the filter is
structured such that the center data value is aligned simultaneously at the A and B inputs of the last ALU in
the forward data path. In order to achieve the correct result, the user must divide the coefficient by two.
Data Reversal
Data reversal circuitry is placed after the multiplexers which route data from the forward data path to the
reverse data path (see Figure 6). When decimating, the data stream must be reversed in order for data to
be properly aligned at the inputs of the ALUs.
Figure 6. Data Reversal
LOGIC Devices Incorporated
5
Video Imaging Products
Feb 5, 2003 LDS.3321-A
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