VITESSE
SEMICONDUCTOR CORPORATION
Preliminary Datasheet
VSC6424
Features
• Multiplex or Demultiplex Operation
• Selectable Shift Register Length
• 500Mb/s Operation using internal timing
• 250Mb/s Operation using external timing
• Functional Replacement for Bt424
• External ECL Reference Voltage (-1.32 V)
500 Mb/s Video
Shift Register IC
• ECL and TTL I/Os: ECL for high-speed interface,
TTL for low-speed interface
• Power Supplies: +3.3V and -2V @ 2.7 Watts (Max.)
• Commercial (0
o
to +70
o
C) Temperature Range
• Package: 14mm x 20mm 128 PQFP
General Description
The VSC6424 is a 500Mb/s video shift register IC that is based on a 40-bit user-configured shift register.
The shift register may be used either as a multiplexer (parallel in, serial out) or as a demultiplexer (serial in, par-
allel out). The VSC6424 can be configured into 8 5-bit, 8 4-bit, 5 8-bit, 4 10-bit, 2 16-bit, 2 20-bit, 1 32-bit, or 1
40-bit shift register.
VSC6424 Functional Block Diagram
ON
E
HBLANK
VBLANK
A<0:4>
AEN/RETIME
(ECL)
5
SIN
40
Input
Latch
(TTL)
40
40
M
UX
8
DOUT<0:7>
High
Speed
Interface
(ECL)
SB<0:39>
Low
Speed
Interface
(TTL)
40-bit
Register
10
DE-
MUX
10
Shift
CLKOUT
Timing Control
S<0:2>
MODE
INT/EXTN
OPS
LLDN
SEN/DIVC
SLDN/SYNC
3
DIN<0:9>
(TTL)
CLK
(ECL)
Clock
Generator
3
Phase
R
otation
CLKE
(ECL)
CLKT
(TTL)
SP<0:2>
G52236-0, Rev 3.0
7/13/99
©
VITESSE
SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
Page 1
VITESSE
SEMICONDUCTOR CORPORATION
500 Mb/s Video
Shift Register IC
Preliminary Datasheet
VSC6424
Functional Description
The VSC6424 is a 40-bit user configurable shift register designed to provide general purpose serialization
or de-serialization for high speed designs. The VSC6424 provides both multiplexer (MUX) and demultiplexer
(DEMUX) operations in a single package. With the ability to generate timing signals internally or have them
provided externally the VSC6424 maintains the highest design flexibility.
The low speed signals (parallel data, configuration, external timing) use a TTL interface and the high-speed
signals (serial data, high-speed clock) use an ECL interface. Two power supplies are utilized, +3.3 Volts and -2
Volts, dissipating a maximum of 2.7 Watts. A -1.32V external reference voltage is necessary for the ECL inter-
face. The part is packaged in a 14mm x 20mm 128-pin plastic quad flat pack with an exposed heat spreader.
Shift Register Mode/Modulus Selection
The shift register can be setup to work as multiplexer or as a demultiplexer. The MODE pin controls the
direction of operation (MUX or DEMUX). The select pins S<0:2> put the shift register in one of 8 configura-
tions shown in Table 1
Table 1: Modulus of Operation
S2
0
0
0
0
1
1
1
1
S1
0
0
1
1
0
0
1
1
S0
0
1
0
1
0
1
0
1
Multiplexer
MODE = 0
8 4:1
8 5:1
5 8:1
4 10:1
2 16:1
2 20:1
1 32:1
1 40:1
Demultiplexer
MODE = 1
10 1:4
8 1:5
5 1:8
4 1:10
2 1:16
2 1:20
1 1:32
1 1:40
Internal Timing
The VSC6424 can be set up to use either internal or external timing sources. The VSC6424 contains an
internal timing generator that provides load and output rates depending on the modulus selected for the shift
register. The timing generator takes an external high speed differential clock (CLK). Internal timing mode must
be used for designs above 250MHz.
The internal timing generator also provides two low-speed clock outputs, CLKT(TTL) and CLKE(ECL).
The low speed clock is brought out so that other ICs can use this to latch the low speed data while in DMUX
mode. The slow speed clock output can be the same as the internal clock, or 1/2 the internal frequency by set-
ting DIVC high. These outputs can also be shifted in 45 degree increments, using the
phase select
pins
SP<0:2>, to allow compensation for trace delays on the board. Phase rotation is not available in divide by 5 or
divide by 10 modes.
The internal high speed clock is also brought out to a differential ECL output (CLKOUT). This output is
provided for clocking of the high speed data into the next IC.
Page 2
©
VITESSE
SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
G52236-0, Rev 3.0
7/13/99
VITESSE
SEMICONDUCTOR CORPORATION
Preliminary Datasheet
VSC6424
500 Mb/s Video
Shift Register IC
The Output Phase Shift (OPS) signal gives the capability of selecting which edge of the high speed clock
the DOUT data is synchronized to. When
OPS
is low,
DOUT
comes out on the rising edge of
CLK.
When
OPS
is high,
DOUT
comes out on the falling edge of
CLK.
The high speed output clock (CLKOUT) is not affected by
the state of
OPS.
External Timing
To provide a functional replacement for older designs using the Bt424, formerly manufactured by Brook-
Tree, the VSC6424 provides an external timing mode. This can be accomplished by setting the INT/EXTN pin
low to bypass the internal timing generator. In this case the load and shift timing signals are provided through
the Shift Enable(SEN), Shift Register Load Control(SLDN), and the Latch Load Control(LLDN) pins.
The VSC6424 has two cycles of propagation delay in multiplexer mode where the Bt424 only has one. This
provides the ability to control on which edge of the output clock the output data is clocked on. With the Output
Phase Select (OPS) pin low the output data (DOUT) is synchronous with the positive edge of CLKOUT, where
if OPS is high the output data is synchronous to the negative edge of CLKOUT. See Figure 6 for a timing dia-
gram example with OPS low.
The shift register can also be loaded with serial data while in external timing mode. This is accomplished by
inputting data into the shift register through the Serial Input (SIN) pin. The data is latched on the rising edge of
the CLK while SLDN is high and SEN is low. The data is then shifted to the output pins on each clock cycle
once Shift Enable (SEN) is set high.
I/O Mapping
There are 10 high speed ECL data inputs and 8 high speed ECL data outputs. Some configurations of oper-
ation do not use all these inputs and outputs. The state of the outputs not being used in a given mode is not guar-
anteed. The following two tables, Table 2 and Table 3, show how the high speed bus (DOUT or DIN) maps to
the low speed bus (SB) for a given configuration.
Data is taken and supplied LSB first. The numbers in the table cells refers to the data bit on the low speed
bus (SB<0:39>). They are the inputs in MUX mode and the outputs in DEMUX mode.
Table 2: MUX Mode SB to DOUT Cross Reference
S<2:0>
000
001
010
011
100
101
110
111
Modulus
8 4:1
8 5:1
5 8:1
4 10:1
2 16:1
2 20:1
1 32:1
1 40:1
DOUT7
28-31
35-39
32-39
DOUT6
24-27
30-34
24-31
30-39
16-32
DOUT5
20-23
25-29
DOUT4
16-19
20-24
16-23
20-29
20-39
DOUT3
12-15
14-19
DOUT2
8-11
10-14
8-15
10-19
0-15
DOUT1
4-7
5-9
DOUT0
0-3
0-4
0-7
0-9
0-19
0-31
0-39
G52236-0, Rev 3.0
7/13/99
©
VITESSE
SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
Page 3
VITESSE
SEMICONDUCTOR CORPORATION
500 Mb/s Video
Shift Register IC
Table 3: DEMUX Mode DIN to SB Cross Reference
S<2:0>
000
001
010
011
100
101
110
111
Preliminary Datasheet
VSC6424
DIN9
36-39
35-39
32-29
30-39
20-39
0-31
0-39
Modulus
10 1:4
8 1:5
5 1:8
4 1:10
2 1:16
2 1:20
1 1:32
1 1:40
DIN8
32-35
30-34
DIN7
28-31
25-29
24-31
20-29
16-32
DIN6
24-27
DIN5
20-23
20-24
16-23
DIN4
16-19
14-19
10-19
DIN3
12-15
10-14
8-15
0-15
DIN2
8-11
DIN1
4-7
5-9
0-7
0-9
DIN0
0-3
0-4
0-19
Initialization
The VSC6424 requires that the SYNC/SLDN input be low for at least one clock cycle after power on, then
be set high for at least on clock period to initialize the device. This is an edge sensitive function. In internal tim-
ing mode this serves to start the internal clock dividers and set the shift register and low speed output clocks in
motion. Additional edges while in internal timing mode serves to synchronize the output clocks as described
below. Once this has been done the device takes (2n) cycles to stabilize. During this time the slow bus (SB)
should be set to zero. The first data is then latched from the slow bus (SB) at the end of the (2n) cycles. The
device is now set to run and will latch data from the slow bus (SB) every (n) cycles. See Table 5 to determine (n)
for a selected modulus.
In MUX mode with internal timing the VSC6424 chip can also be initialized by providing a slow speed
clock to the SYNC input. This slow speed clock must be synchronized with high speed clock and based on the
modulus that the MUX is set to. For example if the VSC6424 is set to 4:1 mode and the high speed clock is set
to 500MHz then the SYNC input must be 125MHz. The initialization at power on will still take (2n) cycles of
the high speed clock. This allows the system to dictate when the slow speed data is latched and where the shift-
ing begins.
In external timing mode the SLDN/SYNC signal serves to set the shift register in motion once the data has
been latched from the slow speed bus.
Page 4
©
VITESSE
SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
G52236-0, Rev 3.0
7/13/99
VITESSE
SEMICONDUCTOR CORPORATION
Preliminary Datasheet
VSC6424
Figure 1: Synchronized VSC6424 Block Diagram
40
VSC6424
SLDN/SYNC
CLKT
500 Mb/s Video
Shift Register IC
120
40
VSC6424
SLDN/SYNC
3 - 30
VSC6424
40
SLDN/SYNC
Synchronization
Several VSC6424 chips can be synchronized together while in internal timing mode by connecting the slow
speed TTL clock output (CLKT) of a master chip to the synchronization input (SYNC) of a slave chip. The inter-
nal timing generator synchronizes to the rising edge of the SYNC input. Given that (n) is the number of high
speed clock cycles for a given modulus mode, synchronization takes two times (n) or (2n) clock cycles to lock
in. If it is necessary to synchronize more than two VSC6424 devices use the TTL clock output (CLKT) from
one chip to drive the SYNC inputs of each of the slave devices. See Figure 2 for a block diagram. See Figure 7
for a timing illustration of the synchronization timing of the slave chip. See Table 5 to determine (n) for a
selected modulus.
In MUX mode multiple VSC6424 chips can also be synchronized by providing a slow speed clock to the
SYNC input on all of the devices. This slow speed clock must be synchronized with high speed clock and based
on the modulus that the MUX is set to. For example if the VSC6424 is set to 8:1 mode and the high speed clock
is set to 400MHz then the SYNC input must be 50MHz.
MPU Address Interface
An
Address Interface
mode translates TTL compatible addresses to ECL compatible output levels. This is
provided for compatibility with the Bt424. When the Address Enable (AEN) signal is low, data from the
Address Line
A<0:4>
TTL input pins is transferred to the
DOUT<0,2,4,6,7>
ECL output pins with one clock
cycle delay. When
AEN
is high, the
A<0:4>
inputs are ignored. The
DOUT<0:7>
data is always synchronized
to
CLK,
regardless of the state of
AEN.
See Figure 9 for a timing illustration of this function.
Video Blanking
The VSC6424 also has a blanking function for video applications. In multiplexer mode, this function allows
zeroing of the high speed outputs (DOUT<0:7>). Setting
HBLANK
or
VBLANK
low drives all
DOUT<0:7>
outputs low synchronously with the clock (CLK). The outputs will be driven low on the modulus boundary. The
outputs are driven low for (n) clock cycles given that (n) is the modulus mode that the chip is set to. See table 4
to determine the value of (n) for a given modulus.
G52236-0, Rev 3.0
7/13/99
©
VITESSE
SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
Page 5
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