NXP Semiconductors
Data sheet: Technical data
Document Number: MMA685x
Rev. 9, 01/2017
MMA685x, Single-axis,
SPI Inertial Sensor
MMA685x, a SafeAssure solution, is a SPI-based, single-axis, medium-g, over-
damped lateral accelerometer designed for use in automotive airbag systems.
Features
•
•
•
•
•
•
•
•
±20
g
to ±120
g
full-scale range
3.3 V or 5 V single supply operation
SPI-compatible serial interface
10-bit digital signed or unsigned SPI data output
Programmable arming functions
12 low-pass filter options, ranging from 50 Hz to 1000 Hz
Optional offset cancellation with > 6 s averaging period and < 0.25 LSB/s slew
rate
Pb-free, 16-Pin QFN, 6 mm x 6 mm x 1.98 mm package
MMA685x
Bottom View
Pb-free 16-Pin QFN
6 mm x 6 mm x 1.98 mm package
Referenced Documents
• AEC-Q100, Revision G, dated May 14, 2007 (http://www.aecouncil.com/)
Ordering information
Device
MMA6851BKCW
MMA6853BKCW
MMA6855BKCW
MMA6856BKCW
MMA6851BKCWR2
MMA6853BKCWR2
MMA6855BKCWR2
MMA6856BKCWR2
Axis
X
X
X
X
X
X
X
X
Axis Range
±25
g
±50
g
±120
g
±60
g
±25
g
±50
g
±120
g
±60
g
Package
98ASA00690D
98ASA00690D
98ASA00690D
98ASA00690D
98ASA00690D
98ASA00690D
98ASA00690D
98ASA00690D
Shipping
Tubes
Tubes
Tubes
Tubes
Tape & Reel
Tape & Reel
Tape & Reel
Tape & Reel
Top View
V
SSA
V
SSA
12 CS
11 MOSI
10 SCLK
9 V
CC
5
N/C
6
ARM/PCM
7
TEST/V
PP
8
MISO
N/C
N/C
16 15 14 13
V
REGA
1
V
SS
2
V
REG
3
V
SS
4
17
Pin connections
© 2017 NXP B.V.
1
1.1
V
CC
General Description
Application Diagram
V
CC
V
REG
V
REGA
CS
SCLK
MOSI
MISO
CS_A
SCLK1
MOSI1
MISO1
CS_D
SCLK2
MOSI2
MISO2
CS
SCLK
MOSI
MISO
C1
C2
C3
MMA685x
V
SSA
V
SS
V
PP
/TEST
ARM
Main MCU
Deployment IC
DEPLOY_EN
Figure 1. Application Diagram
Table 1. External Component Recommendations
Ref Des
C1
C2
C3
Type
Ceramic
Ceramic
Ceramic
Description
0.1
μF,
10 %, 10 V Minimum, X7R
1
μF,
10 %, 10 V Minimum, X7R
1
μF,
10 %, 10 V Minimum, X7R
Purpose
V
CC
Power Supply Decoupling
Voltage Regulator Output Capacitor (C
REG
)
Voltage Regulator Output Capacitor (C
REGA
)
1.2
Device Orientation
xxxxxxx
xxxxxxx
X: 0
g
MMA685x
2
Sensors
NXP Semiconductors
xxxxxxx
xxxxxxx
X: +1
g
TTT
Figure 2. Device Orientation Diagram
MMA685x
BKCW
AWLYWWZ
xxxxxxx
xxxxxxx
X: 0
g
xxxxxxx
xxxxxxx
X: –1
g
X: 0
g
X: 0
g
EARTH GROUND
Data Code Legend:
A: Assembly Location
WL: Wafer Lot Number (g-cell Lot Number)
Y: Year
WW: Work Week
Z: Assembly Lot Number
Figure 3. Part Marking
1.3
Internal Block Diagram
V
PP
V
CC
V
REG
V
SS
Odd Register
Array
SPI
Mismatch
Verification
Odd
Register
SPI
V
REGA
V
SSA
V
REG
V
REGA
V
CC
SPI
I/O
CS
SCLK
MOSI
MISO
Self
Test
Analog
Regulator
8 MHz
Digital
Regulator
1
MHz
Oscillator
Voltage
Monitoring
OTP
Array
Memory
V
REGA
Over-Damped
X-axis
g-Cell
ΣΔ
Converter
Clock & bias
Generator
V
REG
Even Register
Array
Clock CRC
Generation
IIR
SINC Filter
Low-Pass Filter
Compensation
Linear
Interpolation
Clock
Monitoring
Offset
Monitor
Offset
Cancellation
Output
Scaling
Even
Register
SPI
ARM_X
ARM
Figure 4. Block Diagram
MMA685x
Sensors
NXP Semiconductors
3
1.4
Pin Connections
V
SSA
V
SSA
12 CS
11 MOSI
10 SCLK
9 V
CC
5
N/C
6
ARM/PCM
7
TEST/V
PP
8
MISO
Definition
This pin is connected to the power supply for the internal analog circuitry. An external capacitor must be
connected between this pin and V
SSA
. Reference
Figure 1.
This pin is the power supply return node for the digital circuitry.
This pin is connected to the power supply for the internal digital circuitry. An external capacitor must be
connected between this pin and V
SS
. Reference
Figure 1.
This pin is the power supply return node for the digital circuitry.
No Connection
N/C
16 15 14 13
V
REGA
1
V
SS
2
V
REG
3
V
SS
4
17
Figure 5. 16-Pin QFN Package, Top View
Table 2. Pin Description
Pin
1
2
3
4
5
Pin
Name
V
REGA
V
SS
V
REG
V
SS
N/C
Formal Name
Analog
Supply
Digital GND
Digital
Supply
Digital GND
No Connect
6
ARM/
PCM
The function of this pin is configurable via the DEVCFG register as described in
Section 3.1.6.5.
When the
arming output is selected, ARM can be configured as an open drain, active low output with a pullup current; or
Arm Output /
an open drain, active high output with a pulldown current. Alternatively, this pin can be configured as a digital
PCM Output
output with a PCM signal proportional to the acceleration data. Reference
Section 3.8.9
and
Section 3.8.10.
If
unused, this pin must be left unconnected.
Programming This pin provides the power for factory programming of the OTP registers. This pin must be connected to V
SS
Voltage
in the application.
SPI Data Out This pin functions as the serial data output for the SPI port.
Supply
SPI Clock
SPI Data In
Chip Select
This pin supplies power to the device. An external capacitor must be connected between this pin and V
SS
.
Reference
Figure 1.
This input pin provides the serial clock to the SPI port. An internal pulldown device is connected to this pin.
This pin functions as the serial data input to the SPI port. An internal pulldown device is connected to this pin.
This input pin provides the chip select for the SPI port. An internal pullup device is connected to this pin.
7
8
9
10
11
12
13
14
15
16
17
TEST/
V
PP
MISO
V
CC
SCLK
MOSI
CS
V
SSA
N/C
N/C
V
SSA
PAD
Corner
Pads
Analog GND This pin is the power supply return node for analog circuitry.
No Connect
No Connect
No Connection
No Connection
Analog GND This pin is the power supply return node for analog circuitry.
Die Attach
Pad
This pin is the die attach flag, and is internally connected to V
SS
.
Corner Pads The corner pads are internally connected to V
SS
.
MMA685x
4
Sensors
NXP Semiconductors
N/C
2
2.1
#
Electrical Characteristics
Maximum Ratings
Rating
1 Supply Voltage
2 C
REG
, C
REGA
3 SCLK, CS, MOSI, V
PP
/TEST
4 ARM
5 MISO (high impedance state)
6 Acceleration without hitting internal
g-cell
stops
7 Acceleration without saturation of internal circuitry
8 Powered Shock (six sides, 0.5 ms duration)
9 Unpowered Shock (six sides, 0.5 ms duration)
10 Drop Shock (to concrete surface)
Electrostatic Discharge
Human Body Model (HBM)
Charge Device Model (CDM)
Machine Model (MM)
Maximum ratings are the extreme limits to which the device can be exposed without permanently damaging it.
Symbol
V
CC
V
REG
V
IN
V
IN
V
IN
g
gcell_Clip
g
ADC_Clip
g
pms
g
shock
h
DROP
V
ESD
V
ESD
V
ESD
T
stg
q
JC
Value
–0.3 to +7.0
–0.3 to +3.0
–0.3 to V
CC
+ 0.3
–0.3 to V
CC
+ 0.3
–0.3 to V
CC
+ 0.3
±500
±375
±1500
±2000
1.2
±2000
±750
±200
–40 to +125
2.5
Unit
V
V
V
V
V
g
g
g
g
m
(3)
(3)
(3)
(3)
(3)
(3, 18)
(3)
(5, 18)
(5, 18)
(5)
11
12
13
V
V
V
°C
°C/W
(5)
(5)
(5)
(5)
(14)
14 Storage Temperature Range
15 Thermal Resistance - Junction to Case
2.2
#
16
17
18
Operating Range
Characteristic
Supply Voltage
Standard Operating Voltage, 3.3 V
Standard Operating Voltage, 5.0 V
Operating Ambient Temperature Range
Verified by 100 % Final Test
The operating ratings are the limits normally expected in the application and define the range of operation.
Symbol
V
CC
Min
V
L
+3.135
—
T
L
–40
0.000033
Typ
V
TYP
+3.3
+5.0
⎯
⎯
Max
V
H
+5.25
—
T
H
+105
3300
Units
V
V
C
V/μs
(15)
(15)
(1)
(19)
T
A
V
CC_r
20 Power-on Ramp Rate (V
CC
)
MMA685x
Sensors
NXP Semiconductors
5
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