Freescale Semiconductor
Technical Data
Document Number: MMA81XXEG
Rev 5, 04/2010
Digital X-Axis or Z-Axis
Accelerometer
The MMA81XXEG (Z-axis) and MMA82XXEG/MMA82XXTEG (X-axis) are
members of Freescale’s family of DSI 2.0-compatible accelerometers. These
devices incorporate digital signal processing for filtering, trim and data
formatting.
Features
•
Available in 20g, 40g, 150g, and 250g (MMA82XXEG, X-axis),
50g and 100g (MMA82XXTEG, X-axis) and 40g, 100g, 150g, and
250g (MMA81XXEG, Z-axis). Additional g-ranges may be available upon
request
80 customer-accessible OTP bits
10-bit digital data output from 8 to 10 bit DSI output
6.3 to 30 V supply voltage
On-chip voltage regulator
Internal self-test
Minimal external component requirements
RoHS compliant (-40 to +125ºC) 16-pin SOIC package
Automotive AEC-Q100 qualified
DSI 2.0 Compliant
Z-axis transducer is overdamped
MMA81XXEG
MMA82XXEG
MMA82XXTEG
SERIES
SINGLE-AXIS
DSI 2.0
ACCELEROMETER
•
•
•
•
•
•
•
•
•
•
EG SUFFIX (Pb-free)
16-LEAD SOIC
CASE 475-01
PIN CONNECTIONS
Typical Applications
•
•
•
Crash detection (Airbag)
Impact and vibration monitoring
Shock detection.
N/C
N/C
C
REG
V
PP
/TEST
C
FIL
D
OUT
V
GND
/D
IN
CLK
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
SS
V
SS
BUSRTN
BUSIN
BUSOUT
H
CAP
V
SS
C
REG
16-PIN SOIC PACKAGE
© Freescale Semiconductor, Inc., 2009, 2010. All rights reserved.
ORDERING INFORMATION
Device Name
MMA8225EGR2
MMA8225EG
MMA8215EGR2
MMA8215EG
MMA8210TEGR2
MMA8210TEG
MMA8205TEGR2
MMA8205TEG
MMA8204EGR2
MMA8204EG
MMA8202EGR2
MMA8202EG
MMA8125EGR2
MMA8125EG
MMA8115EGR2
MMA8115EG
MMA8110EGR2
MMA8110EG
MMA8104EGR2
MMA8104EG
X-axis g-Level
250
250
150
150
100
100
50
50
40
40
20
20
—
—
—
—
—
—
—
—
Z-axis g-Level
—
—
—
—
—
—
—
—
—
—
—
—
250
250
150
150
100
100
40
40
Temperature Range
-40 to +125°C
-40 to +125°C
-40 to +125°C
-40 to +125°C
-40 to +125°C
-40 to +125°C
-40 to +125°C
-40 to +125°C
-40 to +125°C
-40 to +125°C
-40 to +125°C
-40 to +125°C
-40 to +125°C
-40 to +125°C
-40 to +125°C
-40 to +125°C
-40 to +125°C
-40 to +125°C
-40 to +125°C
-40 to +125°C
SOIC 16 Package
475-01
475-01
475-01
475-01
475-01
475-01
475-01
475-01
475-01
475-01
475-01
475-01
475-01
475-01
475-01
475-01
475-01
475-01
475-01
475-01
Packaging
Tape & Reel
Tubes
Tape & Reel
Tubes
Tape & Reel
Tubes
Tape & Reel
Tubes
Tape & Reel
Tubes
Tape & Reel
Tubes
Tape & Reel
Tubes
Tape & Reel
Tubes
Tape & Reel
Tubes
Tape & Reel
Tubes
SECTION 1 GENERAL DESCRIPTION
MMA81XXEG/MMA82XXEG/MMA82XXTEG family is a satellite accelerometer which is comprised of a single axis, variable ca-
pacitance sensing element with a single channel interface IC. The interface IC converts the analog signal to a digital format which
is transmitted in accordance with the DSI-2.0 specification.
1.1
OVERVIEW
Signal conditioning begins with a Capacitance to Voltage conversion (C to V) followed by a 2-stage switched capacitor amplifier.
This amplifier has adjustable offset and gain trimming and is followed by a low-pass switched capacitor filter with Bessel function.
Offset and gain of the interface IC are trimmed during the manufacturing process. Following the filter the signal passes to the
output stage. The output stage sensitivity incorporates temperature compensation.
The output of the accelerometer signal conditioning is converted to a digital signal by an A/D converter. After this conversion the
resultant digital word is converted to a serial data stream which may be transmitted via the DSI bus. Power for the device is
derived from voltage applied to the BUSIN/BUSOUT and V
SS
pins. Bus voltage is rectified and applied to an external capacitor
connected to the H
CAP
pin. During data transmissions, the device operates from stored charge on the external capacitor. An
integrated regulator supplies fixed voltage to internal circuitry.
A self-test voltage may be applied to the electrostatic deflection plate in the sensing element. Self-Test voltage is factory trimmed.
Other support circuits include a bandgap voltage reference for the bias sources and the self-test voltage.
A total of 128 bits of One-Time Programmable (OTP) memory, are provided for storage of factory trim data, serial number and
device characteristics. Eighty OTP bits are available for customer programming. These eighty OTP bits may be programmed via
the DSI Bus or through the serial test/trim interface. OTP integrity is verified through continuous parity checking. Separate parity
bits are provided for factory and customer programmed data. In the event that a parity fault is detected, the reserved value of
zero is transmitted in response to a Read Acceleration Data command.
A block diagram illustrating the major elements of the device is shown in
Figure 1-1.
MMA81XXEG
2
Sensors
Freescale Semiconductor
REGULATOR
TRIM
11
VOLTAGE
REGULATOR
INTERNAL
SUPPLY
VOLTAGE
9
H
CAP
C
REG
3
12
C
REG
BUSOUT
BUSIN
13
N/C
N/C
1
2
V
SS
V
SS
V
SS
BUSRTN
BANDGAP
REFERENCE
16
15
10
14
GROUND
LOSS
DETECTOR
7
V
GND
/D
IN
OSCILLATOR
SELFTEST
TRIM
OSC
TRIM
SELFTEST
VOLTAGE
LOGIC
COMMAND DECODE
STATE MACHINE
RESPONSE GENERATION
4
OTP
PROGRAMMING
INTERFACE
6
8
V
PP
/TEST
D
OUT
CLK
SELF-TEST ENABLE
A-TO-D
CONVERTER
SWITCHES SHOWN
IN NORMAL OPERATING
CONFIGURATION
g-CELL
C-TO-V
CONVERTER
LOW-PASS
FILTER
5
C
FIL
GAIN
TRIM
OFFSET
TRIM
TCS
TRIM
Figure 1-1. Overall Block Diagram
MMA81XXEG
Sensors
Freescale Semiconductor
3
1.2
PACKAGE PINOUT
The pinout for this 16-pin device is shown in
Figure 1-2.
+Z
N/C
N/C
C
REG
V
PP
/TEST
C
FIL
D
OUT
V
GND
/D
IN
CLK
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
SS
V
SS
BUSRTN
BUSIN
BUSOUT
H
CAP
V
SS
C
REG
+X
-X
-Z
ACTIVATION OF Z-AXIS SELF-TEST
CAUSES OUTPUT TO
BECOME MORE POSITIVE
PROJECTION
16-PIN SOIC PACKAGE
ACTIVIATION OF X-AXIS SELF-TEST
CAUSES OUTPUT TO
BECOME MORE POSITIVE
CASE: 475-01
N/C: NO INTERNAL CONNECTION
Output response to displacement in the direction of arrows.
+1 g
+1 g
0g
0g
0g
0g
-1 g
TO CENTER OF
GRAVITATIONAL FIELD
-1 g
Response to static orientation within 1 g field.
Figure 1-2. Device Pinout
MMA81XXEG
4
Sensors
Freescale Semiconductor
1.3
PIN FUNCTIONS
The following paragraphs provide descriptions of the general function of each pin.
1.3.1
H
CAP
and V
SS
Power is supplied to the ASIC through BUSIN or BUSOUT and BUSRTN. The supply voltage is rectified internally and applied
to the H
CAP
pin. An external capacitor connected to HCAP forms the positive supply for the integrated voltage regulator. V
SS
is
supply return node. All V
SS
pins are internally connected to BUSRTN. To obtain specified performance, all V
SS
nodes should be
connected to the BUSRTN node on the PWB. To ensure stability of the internal voltage regulator and meet DFMEA requirements,
the connection from H
CAP
to the external capacitor should be as short as possible and should not be routed elsewhere on the
printed wiring assembly.
The voltage on H
CAP
is monitored. If the voltage falls below a specified level, the device will return the value zero in response to
a short word Read Acceleration Data command, and report the undervoltage condition by setting the Undervoltage (U) flag.
Should the undervoltage condition persist for more than one millisecond, the internal Power-On Reset (POR) circuit is activated
and the device will not respond until the voltage at H
CAP
is restored to operating levels and the device has undergone post-reset
initialization.
1.3.2
BUSIN
The BUSIN pin is normally connected to the DSI bus and supports bidirectional communication with the master.
The MMA81XXEG, MMA82XXEG and MMA82XXTEG supports reverse initialization for improved system fault tolerance. In the
event that the DSI bus cannot support communication between the master and BUSIN pin, communication with the master may
be conducted via the BUSOUT pin and the BUSIN pin can be used to access other DSI devices.
1.3.3
BUSOUT
The BUSOUT pin is normally connected to the DSI bus for daisy-chained bus configurations. In support of fault tolerance at the
system level, the BUSOUT pin can be used as an input for reverse initialization and data communication.
The internal bus switch is always open following reset. The bus switch is closed when data bit D6 is set when an Initialization or
Reverse Initialization command is received.
1.3.4
BUSRTN
This pin provides the common return for power and signalling.
1.3.5
C
REG
The internal voltage regulator requires external capacitance to the V
SS
pin for stability. This should be a high grade capacitor
without excessive internal resistance or inductance. An optional electrolytic capacitor may be required if a longer power down
delay is required.
Figure 1-3
illustrates the relationship between capacitance, series resistance and voltage regulator stability. Two C
REG
pins are
provided for redundancy. It is recommended that both C
REG
pins are connected to the external capacitor(s) for best system
reliability.
STABLE, UNACCEPTABLE
NOISE PERFORMANCE
700 mΩ
UNSTABLE
ESR
STABLE
0
1
μF
C
REG
Figure 1-3. Voltage Regulator Capacitance and Series Resistance
MMA81XXEG
Sensors
Freescale Semiconductor
5
100
μF
微控制器 MCU
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