IRS2453(1)D(S)
Product Summary
Topology
V
OFFSET
I
o+
& I
o-
(typical)
Deadtime (typical)
Full-bridge
600 V
180 mA & 260 mA
1.0 μs (IRS2453D)
0.5 μs (IRS24531D)
Features
Integrated 600 V full-bridge gate driver
CT, RT programmable oscillator
15.6 V Zener clamp on V
CC
Micropower startup
Logic level latched shutdown pin
Non-latched shutdown on CT pin (1/6th V
CC
)
Internal bootstrap FETs
Excellent latch immunity on all inputs & outputs
ESD protection on all pins
14-lead SOIC or PDIP package
0.5 or 1.0μs (typ.) internal dead time
RoHS compliant
Package Options
14 Lead PDIP
IRS2453DPbF
14 Lead SOIC
(Narrow Body)
IRS2453(1)DSPbF
Ordering Information
Standard Pack
Base Part Number
Package Type
Form
PDIP14
IRS2453D(S)
SOIC14N
Tape and Reel
Tube/Bulk
IRS24531DS
SOIC14N
Tape and Reel
2500
IRS24531DSTRPBF
2500
55
IRS2453DSTRPBF
IRS24531DSPBF
Tube/Bulk
Tube/Bulk
Quantity
25
55
IRS2453DPBF
IRS2453DSPBF
Complete Part Number
1
www.irf.com
© 2016 International Rectifier
April 27, 2016
IRS2453(1)D(S)
Table of Contents
Ordering Information
Description
Typical Connection Diagram
Qualification Information
Absolute Maximum Ratings
Recommended Operating Conditions
Recommended Component Values
Electrical Characteristics
Functional Block Diagram
Input / Output Pin Equivalent Circuit Diagram
Lead Definitions
Lead Assignments
Application Information and Additional Details
Package Details
Tape and Reel Details
Part Marking Information
Page
1
3
3
4
5
6
6
7
9
10
11
11
12
15
16
17
2
www.irf.com
© 2016 International Rectifier
April 27, 2016
IRS2453(1)D(S)
Description
The IRS2453(1)D is based on the popular IR2153 self-oscillating half-bridge gate driver IC, and incorporates a
high voltage full-bridge gate driver with a front end oscillator similar to the industry standard CMOS 555 timer.
HVIC and latch immune CMOS technologies enable ruggedized monolithic construction. The output driver
features a high pulse current buffer stage designed for minimum driver cross-conduction. Noise immunity is
achieved with low di/dt peak of the gate drivers, and with an under voltage lockout hysteresis greater than 1.5 V.
The IRS2453(1)D also includes latched and non-latched shutdown pins.
Typical Connection Diagram
+ AC rectified line
15 V
1
VCC
VB1
14
IRS2453(1)D
2
COM
3
CT
4
RT
5
SD
6
LO1
7
LO2
HO1
13
VS1
12
NC
11
VB2
10
HO2
9
VS2
8
LOAD
- AC rectified line
3
www.irf.com
© 2016 International Rectifier
April 27, 2016
IRS2453(1)D(S)
Qualification Information
Qualification Level
†
††
Moisture Sensitivity Level
Machine Model
ESD
Human Body Model
IC Latch-Up Test
RoHS Compliant
†
††
†††
Industrial
Comments: This family of ICs has passed JEDEC’s
Industrial qualification. IR’s Consumer qualification level is
granted by extension of the higher Industrial level.
†††
MSL2 260°C
SOIC14
(per IPC/JEDEC J-STD-020)
Not applicable
PDIP14
(non-surface mount package style)
Class C
(per JEDEC standard JESD22-A115)
Class 2
(per EIA/JEDEC standard EIA/JESD22-A114)
Class I, Level A
(per JESD78)
Yes
Qualification standards can be found at International Rectifier’s web site
http://www.irf.com/
Higher qualification ratings may be available should the user have such requirements. Please contact
your International Rectifier sales representative for further information.
Higher MSL ratings may be available for the specific package types listed here. Please contact your
International Rectifier sales representative for further information.
4
www.irf.com
© 2016 International Rectifier
April 27, 2016
IRS2453(1)D(S)
Absolute Maximum Ratings
Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage
parameters are absolute voltages referenced to COM, all currents are defined positive into any lead. The thermal
resistance and power dissipation ratings are measured under board mounted and still air conditions.
Symbol
Definition
Min.
Max.
Units
VB1,
High side floating supply voltage
-0.3
625
VB2
VS1,
VB - 25
VB + 0.3
High side floating supply offset voltage
VS2
V
HO1
,
VS - 0.3
VB + 0.3
High side floating output voltage
V
HO2
V
V
LO1
,
VCC + 0.3
Low side output voltage
-0.3
V
LO2
VRT
RT pin voltage
VCC + 0.3
-0.3
VCT
VSD
IRT
ICC
dV
S
/dt
PD
PD
R
θJA
R
θJA
TJ
TS
TL
†
CT pin voltage
SD pin voltage
RT pin current
Supply current (†)
Allowable offset voltage slew rate
Maximum power dissipation @ T
A
≤ +25 ºC, PDIP14
Maximum power dissipation @ T
A
≤ +25 ºC, SOIC14N
Thermal resistance, junction to ambient, PDIP14
Thermal resistance, junction to ambient, SOIC14N
Junction temperature
Storage temperature
Lead temperature (soldering, 10 seconds)
-0.3
-0.3
-5
---
-50
---
---
---
---
-55
-55
---
VCC + 0.3
VCC + 0.3
5
25
50
1.6
1.0
75
120
150
150
300
ºC
ºC/W
W
mA
V/ns
This IC contains a zener clamp structure between the chip VCC and COM which has a nominal
breakdown voltage of 15.6 V. Please note that this supply pin should not be driven by a DC, low
impedance power source greater than the VCLAMP specified in the Electrical Characteristics section.
5
www.irf.com
© 2016 International Rectifier
April 27, 2016
微控制器 MCU
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
