2.5 V, 3.3 V Differential LVPECL
Clock Divider and Fanout Buffer
8T73S208
Datasheet
General Description
The 8T73S208 is a high-performance differential LVPECL clock
divider and fanout buffer. The device is designed for the frequency
division and signal fanout of high-frequency, low phase-noise clocks.
The 8T73S208 is characterized to operate from a 2.5V and 3.3V
power supply. Guaranteed output-to-output and part-to-part skew
characteristics make the 8T73S208 ideal for those clock distribution
applications demanding well-defined performance and repeatability.
The integrated input termination resistors make interfacing to the
reference source easy and reduce passive component count. Each
output can be individually enabled or disabled in the high-impedance
state controlled by a I
2
C register. On power-up, all outputs are
enabled.
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
•
One differential input reference clock
Differential pair can accept the following differential input
levels: LVDS, LVPECL, CML
Integrated input termination resistors
Eight LVPECL outputs
Selectable clock frequency division of ÷1, ÷2, ÷4 and ÷8
Maximum input clock frequency: 1000MHz
LVCMOS interface levels for the control inputs
Individual output enable/disabled by I
2
C interface
Output skew: 15ps (typical)
Output rise/fall times: 350ps (maximum)
Low additive phase jitter, RMS: 0.182ps (typical)
Full 2.5V and 3.3V supply voltages
Lead-free (RoHS 6) 32-Lead VFQFN packaging
-40°C to 85°C ambient operating temperature
Block Diagram
Q0
nQ0
Q1
nQ1
f
REF
Pin Assignment
FSEL0
V
CCO
17
16
15
14
nQ7
nQ6
V
EE
24
23
22
21
20
19
FSEL1
IN
V
T
nIN
V
CC
25
26
27
28
29
30
31
32
1
2
3
4
5
6
7
8
V
EE
18
Q7
Q6
nQ5
Q5
nQ4
Q4
nQ3
Q3
nQ2
Q2
IN
nIN
50
50
÷1, ÷2,
÷4, ÷8
Q2
nQ2
Q3
nQ3
VT
FSEL[1:0]
Pulldown (2)
2
8T73S208
13
12
11
10
9
Q4
nQ4
Q5
nQ5
8
Q6
nQ6
Q7
nQ7
SDA
SCL
ADR0
2
©2016 Integrated Device Technology, Inc.
1
ADR1
32-pin, 5mm x 5mm VFQFN
Revision D, June 15, 2016
V
CCO
V
EE
nQ0
nQ1
V
EE
Q0
Q1
SDA
SCL
ADR[1:0]
Pullup
Pullup
Pulldown (2)
I C
2
8T73S208 Datasheet
Pin Description and Pin Characteristic Tables
Table 1. Pin Descriptions
Number
1,
32
2, 7, 18, 23
3, 4
5, 6
8, 17
9, 10
11, 12
13, 14
15, 16
19, 20
21, 22
24,
25
26
27
28
29
30
31
Name
ADR1, ADR0
V
EE
Q0, nQ0
Q1, nQ1
V
CCO
Q2, nQ2
Q3, nQ3
Q4, nQ4
Q5, nQ5
Q6, nQ6
Q7, nQ7
FSEL0,
FSEL1
IN
V
T
nIN
V
CC
SDA
SCL
Input
Power
Output
Output
Power
Output
Output
Output
Output
Output
Output
Input
Input
Termination
Input
Input
Power
I/O
Input
Pullup
Pullup
Pulldown
Type
Pulldown
Description
I
2
C Address inputs. LVCMOS/LVTTL interface levels.
Negative supply pins.
Differential output pair 0. LVPECL interface levels.
Differential output pair 1. LVPECL interface levels.
Output supply pins.
Differential output pair 2. LVPECL interface levels.
Differential output pair 3. LVPECL interface levels.
Differential output pair 4. LVPECL interface levels.
Differential output pair 5. LVPECL interface levels.
Differential output pair 6. LVPECL interface levels.
Differential output pair 7. LVPECL interface levels.
Frequency divider select controls. See Table 3A for function.
LVCMOS/LVTTL interface levels.
Non-inverting differential clock input. RT = 50 termination to V
T.
Input for termination. Both IN and nIN inputs are internally terminated 50
to this pin. See input termination information in the applications section.
Inverting differential clock input. RT = 50 termination to V
T.
Power supply pin.
I
2
C Data Input/Output. Input: LVCMOS/LVTTL interface levels. Output:
open drain.
I
2
C Clock Input. LVCMOS/LVTTL interface levels.
NOTE:
Pulldown
and
Pullup
refers to an internal input resistors. See Table 2,
Pin Characteristics,
for typical values.
Table 2. Pin Characteristics
Symbol
C
IN
R
PULLDOWN
R
PULLUP
Parameter
Input Capacitance
Input Pulldown Resistor
Input Pullup Resistor
Test Conditions
Minimum
Typical
2
51
51
Maximum
Units
pF
k
k
©2016 Integrated Device Technology, Inc.
2
Revision D, June 15, 2016
8T73S208 Datasheet
Function Tables
Input Frequency Divider Operation
The FSEL1 and FSEL0 control pins configure the input frequency
divider. In the default state (FSEL[1:0] are set to logic 0:0 or left open)
the output frequency is equal to the input frequency (divide-by-1).
The other FSEL[1:0] settings configure the input divider to
divide-by-2, 4 or 8, respectively.
Table 3A. FSEL[1:0] Input Selection Function Table
Input
FSEL1
0 (default)
0
1
1
FSEL0
0 (default)
1
0
1
Operation
f
Q[7:0]
= f
REF
÷ 1
f
Q[7:0]
= f
REF
÷ 2
f
Q[7:0]
= f
REF
÷ 4
f
Q[7:0]
= f
REF
÷ 8
SCL
acknowledge or Not-Acknowledge bit and the stop bit. These
elements are arranged to make up the complete I
2
C transactions as
shown in Figure 2 and Figure 3. Figure 2 is a write transaction while
Figure 3 is read transaction. The 7-bit I
2
C slave address of the
8T73S208 is a combination of a 4-bit fixed addresses and two
variable bits which are set by the hardware pins ADR[1:0] (binary
11010, ADR1, ADR0). Bit 0 of slave address is used by the bus
controller to select either the read or write mode. The hardware pins
ADR1 and ADR0 and should be individually set by the user to avoid
address conflicts of multiple 8T73S208 devices on the same bus.
Table 3D. I
2
C Slave Address
7
1
6
1
5
0
4
1
3
0
2
ADR1
1
ADR0
0
R/W
NOTE: FSEL1, FSEL0 are asynchronous controls
Output Enable Operation
The output enable/disable state of each individual differential output
Qx, nQx can be set by the content of the I
2
C register (see Table 3C).
A logic zero to an I
2
C bit in register 0 enables the corresponding
differential output, while a logic one disables the differential output
(see Table 3B). After each power cycle, the device resets all I
2
C bits
(Dn) to its default state (logic 0) and all Qx, nQx outputs are enabled.
After the first valid I
2
C write, the output enable state is controlled by
the I
2
C register. Setting and changing the output enable state through
the I
2
C interface is asynchronous to the input reference clock.
The device supports the enable/disable of individual outputs.
During an active operation of the device, enabling individual
previously disabled outputs may degrade signal integrity of already
enabled active outputs during the enabling transition. Disabling
multiple outputs is supported without signal integrity constraints.
Table 3B. Individual Output Enable Control
Bit
Dn
0 (default)
1
Operation
Output Qx, nQx is enabled.
Output Qx, nQx is disabled in high-impedance
state.
SDA
START
Valid Data
Acknowledge
STOP
Figure 1: Standard I
2
C Transaction
START (S)
– defined as high-to-low transition on SDA while holding
SCL HIGH.
DATA
– between START and STOP cycles, SDA is synchronous with
SCL. Data may change only when SCL is LOW and must be stable
when SCL is HIGH.
ACKNOWLEDGE (A)
– SDA is driven LOW before the SCL rising
edge and held LOW until the SCL falling edge.
STOP (S)
– defined as low-to-high transition on SDA while holding
SCL HIGH
S
DevAdd
W A
Data Byte
A P
Figure 2: Write Transaction
Table 3C. Individual output enable control
Bit
Output
Default
D7
Q7
0
D6
Q6
0
D5
Q5
0
D4
Q4
0
D3
Q3
0
D2
Q2
0
D1
Q1
0
D0
Q0
0
S DevAdd R A
Data Byte
Figure 3: Read Transaction
S
–
W
–
R
–
Start or Repeated Start
R/~W is set for Write
R/~W is set for Read
Ack
7 bit Device Address
Stop
A P
I
2
C Interface Protocol
I
2
C
The IDT8T73S208I uses an
slave interface for writing and
reading the device configuration to and from the on-chip
configuration registers. This device uses the standard I
2
C write
format for a write transaction, and a standard I
2
C read format for a
read transaction. Figure 1 defines the I
2
C elements of the standard
I
2
C transaction. These elements consist of a start bit, data bytes, an
A
–
DevAdd
–
P
–
©2016 Integrated Device Technology, Inc.
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Revision D, June 15, 2016
8T73S208 Datasheet
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under
Absolute Maximum Ratings
may cause permanent damage to the device. These ratings are stress
specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the
DC Characteristics or AC
Characteristics
is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Item
Supply Voltage, V
CC
Inputs, V
I
Input Termination Current, I
VT
Outputs, I
O
(LVPECL)
Continuous Current
Surge Current
Package Thermal Impedance,
JA
Storage Temperature, T
STG
Maximum Junction Temperature, TJ
MAX
ESD - Human Body Model
1
ESD - Charged Device Model
1
NOTE 1. According to JEDEC/JS-001-2012-KJESD22- 22-C101E.
Rating
4.6V
-0.5V to V
CC
+ 0.5V
±35mA
50mA
100mA
42.7°C/W (0 mps)
-65C to 150C
125°C
2000V
500V
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics, V
CC
= V
CCO
= 2.5V ± 5% or 3.3V ± 5%, V
EE
= 0V, T
A
= -40°C to 85°C
Symbol
V
CC
V
CC
V
CCO
V
CCO
I
EE
Parameter
Power Supply Voltage
Power Supply Voltage
Output Supply Voltage
Output Supply Voltage
Power Supply Current
Test Conditions
Minimum
2.375
3.135
2.375
3.135
Typical
2.5V
3.3V
2.5V
3.3V
Maximum
2.625
3.465
2.625
3.465
95
Units
V
V
V
V
mA
Table 4B. LVCMOS/LVTTL Input DC Characteristics, V
CC
= V
CCO
= 2.5V ± 5% or 3.3V ± 5%, V
EE
= 0V, T
A
= -40°C to 85°C
Symbol
V
IH
V
IL
I
IH
Parameter
Input High Voltage
Input Low Voltage
Input High
Current
FSEL[1:0],
ADR[1:0]
SCL, SDA
Input Low
Current
FSEL[1:0],
ADR[1:0]
SCL, SDA
V
CC
= V
IN
= 2.625 or 3.465V
V
CC
= V
IN
= 2.625 or 3.465V
V
CC
= 2.625 or 3.465V, V
IN
= 0V
V
CC
= 2.625 or 3.465V, V
IN
= 0V
-10
-150
Test Conditions
Minimum
2.2
-0.3
Typical
Maximum
V
CC
+ 0.3
0.8
150
10
Units
V
V
µA
µA
µA
µA
I
IL
©2016 Integrated Device Technology, Inc.
4
Revision D, June 15, 2016
8T73S208 Datasheet
Table 4C. DC Characteristics,
V
CC
= V
CCO
= 2.5V ± 5% or 3.3V ± 5%, V
EE
= 0V, T
A
= -40°C to 85°C
Symbol
V
IN
V
IH
V
IH
V
IL
V
DIFF_IN
R
IN
R
IN_DIFF
Parameter
Input Voltage Swing
1
Input
High Voltage
Input
High Voltage
Input
Low Voltage
IN, nIN
IN, nIN
IN, nIN
VIN<=1V
VIN>1V
Test Conditions
Minimum
0.15
1.2
1.4
0
0.3
IN to VT
IN to nIN, VT = open
40
80
50
100
60
120
V
CC
V
CC
V
IH
– 0.15
Typical
Maximum
Units
V
V
V
V
V
Differential Input Voltage
Swing
Input Resistance
Differential Input
Resistance
IN, nIN
IN, nIN
NOTE 1. Refer to Parameter Measurement Information, Input Voltage Swing diagram.
Table 4D. LVPECL DC Characteristics,
V
CC
= V
CCO
= 3.3V ± 5%, V
EE
= 0V, T
A
= -40°C to 85°C
Symbol
V
OH
V
OL
V
SWING
Parameter
Output High Voltage
1
Output Low Voltage
1
Peak-to-Peak
Output Voltage Swing
Test Conditions
Minimum
V
CCO
– 1.102
V
CCO
– 1.802
0.60
Typical
V
CCO
– 0.95
V
CCO
– 1.6
0.65
Maximum
V
CCO
– 0.775
V
CCO
– 1.367
1.00
Units
V
V
V
NOTE 1. Outputs terminated with 50 to V
CCO
– 2V.
Table 4E. LVPECL DC Characteristics,
V
CC
= V
CCO
= 2.5V ± 5%, V
EE
= 0V, T
A
= -40°C to 85°C
Symbol
V
OH
V
OL
V
SWING
Parameter
Output High Voltage
1
Output Low Voltage
1
Peak-to-Peak Output
Voltage Swing
Test Conditions
Minimum
V
CCO
– 1.125
V
CCO
– 1.799
0.60
Typical
V
CCO
– 0.95
V
CCO
– 1.6
0.65
Maximum
V
CCO
– 0.767
V
CCO
– 1.359
1.00
Units
V
V
V
NOTE 1. Outputs terminated with 50 to V
CCO
– 2V.
©2016 Integrated Device Technology, Inc.
5
Revision D, June 15, 2016
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