STW12N150K5
N-channel 1500 V, 1.6 Ω typ.,7 A MDmesh™ K5
Power MOSFET in a TO-247 package
Datasheet - production data
Features
Order code
STW12N150K5
V
DS
1500 V
R
DS(on)
max.
1.9 Ω
I
D
P
TOT
7 A 250 W
3
2
1
Industry’s lowest R
DS(on) *
area
Industry’s best figure of merit (FoM)
Ultra low gate charge
100% avalanche tested
Zener-protected
TO-247
Applications
Switching applications
Figure 1: Internal schematic diagram
Description
This very high voltage N-channel Power
MOSFET is designed using MDmesh™ K5
technology based on an innovative proprietary
vertical structure. The result is a dramatic
reduction in on-resistance and ultra-low gate
charge for applications requiring superior power
density and high efficiency.
Table 1: Device summary
Order code
STW12N150K5
Marking
12N150K5
Package
TO-247
Packing
Tube
July 2015
DocID027833 Rev 3
1/13
www.st.com
This is information on a product in full production.
Contents
STW12N150K5
Contents
1
2
3
4
5
Electrical ratings ............................................................................. 3
Electrical characteristics ................................................................ 4
2.1
Electrical characteristics (curves) ...................................................... 6
Test circuits ..................................................................................... 9
Package information ..................................................................... 10
4.1
TO-247 package information ........................................................... 10
Revision history ............................................................................ 12
2/13
DocID027833 Rev 3
STW12N150K5
Electrical ratings
1
Electrical ratings
Table 2: Absolute maximum ratings
Symbol
V
GS
I
D
I
D
I
DM
(1)
Parameter
Gate-source voltage
Drain current at T
C
= 25 °C
Drain current at T
C
= 100 °C
Drain current (pulsed)
Total dissipation at T
C
= 25 °C
Peak diode recovery voltage slope
MOSFET dv/dt ruggedness
Operating junction temperature
Storage temperature
Value
± 30
7
4
28
250
4.5
50
- 55 to 150
Unit
V
A
A
A
W
V/ns
V/ns
°C
P
TOT
dv/dt
dv/dt
T
j
T
stg
Notes:
(1)
(2)
(3)
(2)
(3)
Pulse width limited by safe operating area
I
SD
≤ 7 A, di/dt ≤ 100 A/µs, V
Peak
≤ V
(BR)DSS
V
DS
≤ 1200 V
Table 3: Thermal data
Symbol
R
thj-case
R
thj-amb
Parameter
Thermal resistance junction-case
Thermal resistance junction-amb
Table 4: Avalanche characteristics
Symbol
I
AR
E
AS
Parameter
Max current during repetitive or single pulse avalanche
Single pulse avalanche energy
Value
2
900
Unit
A
mJ
Value
0.5
50
Unit
°C/W
°C/W
DocID027833 Rev 3
3/13
Electrical characteristics
STW12N150K5
2
Electrical characteristics
(T
CASE
= 25 °C unless otherwise specified)
Table 5: On/off states
Symbol
V
(BR)DSS
Parameter
Drain-source breakdown
voltage
Zero gate voltage drain
current
Gate body leakage current
Gate threshold voltage
Static drain-source on-
resistance
Test conditions
V
GS
= 0 V, I
D
= 1 mA
V
GS
= 0 V, V
DS
= 1500 V
V
GS
= 0 V, V
DS
= 1500 V,
Tc=125 °C
V
DS
= 0, V
GS
= ± 20 V
V
DS
= V
GS
, I
D
= 100 µA
V
GS
= 10 V, I
D
= 3.5 A
3
4
1.6
Min.
1500
1
50
±10
5
1.9
Typ.
Max.
Unit
V
µA
µA
µA
V
Ω
I
DSS
I
GSS
V
GS(th)
R
DS(on)
Table 6: Dynamic
Symbol
C
iss
C
oss
C
rss
C
o(tr)
(1)
Parameter
Input capacitance
Output capacitance
Reverse transfer
capacitance
Equivalent capacitance time
related
Equivalent capacitance
energy related
Intrinsic gate resistance
Total gate charge
Gate-source charge
Gate-drain charge
Test conditions
Min.
-
Typ.
1360
80
0.7
82
32
3
47
8
32
Max.
-
-
-
-
-
-
-
-
-
Unit
pF
pF
pF
pF
pF
Ω
nC
nC
nC
V
GS
= 0 V, V
DS
= 100 V,
f = 1MHz
-
-
-
-
-
-
-
-
C
o(er)
R
G
Q
g
(2)
V
DS
= 0 V to 1200 V,
V
GS
= 0 V
f = 1 MHz, I
D
= 0 A
V
DD
= 1200V, I
D
= 7 A
V
GS
= 10 V
(see
Figure 16: "Gate charge
test circuit")
Q
gs
Q
gd
Notes:
(1)
Time related is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS
increases from 0 to 80% VDSS.
(2)
Energy related is defined as a constant equivalent capacitance giving the same stored energy as Coss when
VDS increases from 0 to 80% VDSS.
4/13
DocID027833 Rev 3
STW12N150K5
Table 7: Switching times
Symbol
t
d(on)
t
r
t
d(off)
t
f
Parameter
Turn-on delay
time
Rise time
Turn-off delay
time
Fall time
Table 8: Source drain diode
Symbol
I
SD
I
SDM
V
SD
t
rr
Q
rr
I
RRM
t
rr
Q
rr
I
RRM
Notes:
(1)
(1)
Electrical characteristics
Test conditions
Min.
-
V
DD
= 750 V, I
D
= 3.5 A, R
G
= 4.7 Ω
V
GS
= 10 V
(see
Figure 18: "Unclamped inductive
load test circuit")
-
-
-
Typ.
25
8
90
37
Max.
-
-
-
-
Unit
ns
ns
ns
ns
Parameter
Source-drain
current
Source-drain
current (pulsed)
Forward on
voltage
Reverse recovery
time
Reverse recovery
charge
Reverse recovery
current
Reverse recovery
time
Reverse recovery
charge
Reverse recovery
current
Test conditions
Min.
-
-
Typ.
Max.
7
28
1.5
Unit
A
A
V
ns
µC
A
ns
µC
A
I
SD
= 7 A, V
GS
= 0 V
I
SD
= 7 A, V
DD
= 60 V
di/dt = 100 A/µs,
(see
Figure 17: "Test circuit for
inductive load switching and diode
recovery times")
I
SD
= 7 A,V
DD
= 60 V
di/dt = 100 A/µs,
Tj = 150 °C
(see
Figure 17: "Test circuit for
inductive load switching and diode
recovery times")
-
-
-
-
-
-
-
302
3.71
24.6
432
4.71
21.8
Pulsed: pulse duration = 300µs, duty cycle 1.5%
Table 9: Gate-source Zener diode
Symbol
V(BR)GSO
Parameter
Gate-source breakdown voltage
Test conditions
I
GS
= ±1 mA, I
D
= 0 A
Min.
30
Typ.
-
Max.
Unit
V
The built-in back-to-back Zener diodes have been specifically designed to enhance the
ESD capability of the device. The Zener voltage is appropriate for efficient and cost-
effective intervention to protect the device integrity. These integrated Zener diodes thus
eliminate the need for external components.
DocID027833 Rev 3
5/13
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