or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
www.latticesemi.com
1-1
DS1002 Introduction_01.5
Introduction
MachXO Family Data Sheet
The devices use look-up tables (LUTs) and embedded block memories traditionally associated with FPGAs for flex-
ible and efficient logic implementation. Through non-volatile technology, the devices provide the single-chip, high-
security, instant-on capabilities traditionally associated with CPLDs. Finally, advanced process technology and
careful design will provide the high pin-to-pin performance also associated with CPLDs.
The ispLEVER
®
design tools from Lattice allow complex designs to be efficiently implemented using the MachXO
family of devices. Popular logic synthesis tools provide synthesis library support for MachXO. The ispLEVER tools
use the synthesis tool output along with the constraints from its floor planning tools to place and route the design in
the MachXO device. The ispLEVER tool extracts the timing from the routing and back-annotates it into the design
for timing verification.
1-2
MachXO Family Data Sheet
Architecture
June 2013
Data Sheet DS1002
Architecture Overview
The MachXO family architecture contains an array of logic blocks surrounded by Programmable I/O (PIO). Some
devices in this family have sysCLOCK PLLs and blocks of sysMEM™ Embedded Block RAM (EBRs). Figures 2-1,
2-2, and 2-3 show the block diagrams of the various family members.
The logic blocks are arranged in a two-dimensional grid with rows and columns. The EBR blocks are arranged in a
column to the left of the logic array. The PIO cells are located at the periphery of the device, arranged into Banks.
The PIOs utilize a flexible I/O buffer referred to as a sysIO interface that supports operation with a variety of inter-
face standards. The blocks are connected with many vertical and horizontal routing channel resources. The place
and route software tool automatically allocates these routing resources.
There are two kinds of logic blocks, the Programmable Functional Unit (PFU) and the Programmable Functional
unit without RAM (PFF). The PFU contains the building blocks for logic, arithmetic, RAM, ROM, and register func-
tions. The PFF block contains building blocks for logic, arithmetic, ROM, and register functions. Both the PFU and
PFF blocks are optimized for flexibility, allowing complex designs to be implemented quickly and effectively. Logic
blocks are arranged in a two-dimensional array. Only one type of block is used per row.
In the MachXO family, the number of sysIO Banks varies by device. There are different types of I/O Buffers on dif-
ferent Banks. See the details in later sections of this document. The sysMEM EBRs are large, dedicated fast mem-
ory blocks; these blocks are found only in the larger devices. These blocks can be configured as RAM, ROM or
FIFO. FIFO support includes dedicated FIFO pointer and flag “hard” control logic to minimize LUT use.
The MachXO registers in PFU and sysI/O can be configured to be SET or RESET. After power up and device is
configured, the device enters into user mode with these registers SET/RESET according to the configuration set-
ting, allowing device entering to a known state for predictable system function.
The MachXO architecture provides up to two sysCLOCK™ Phase Locked Loop (PLL) blocks on larger devices.
These blocks are located at either end of the memory blocks. The PLLs have multiply, divide, and phase shifting
capabilities that are used to manage the frequency and phase relationships of the clocks.
Every device in the family has a JTAG Port that supports programming and configuration of the device as well as
access to the user logic. The MachXO devices are available for operation from 3.3V, 2.5V, 1.8V, and 1.2V power
supplies, providing easy integration into the overall system.
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
www.latticesemi.com
2-1
DS1002
Architecture_01.5
Architecture
MachXO Family Data Sheet
Figure 2-1. Top View of the MachXO1200 Device
1
PIOs Arranged into
sysIO Banks
sysMEM Embedded
Block RAM (EBR)
Programmable
Functional Units
with RAM (PFUs)
Programmable
Functional Units
without RAM (PFFs)
sysCLOCK
PLL
JTAG Port
1. Top view of the MachXO2280 device is similar but with higher LUT count, two PLLs, and three EBR blocks.
主题：自备终端(BYOD)发展趋势;用员工自己的移动设备来控制对工作设施及设备的使用，会对信息安全产生怎样的影响;在不使公司有安全风险或不损害员工隐私的前提下，有哪些方式能安全地实现这样的设施及设备使用。 自备终端(Bring Your Own Device，简称BYOD)，即企业允许员工离职时保留自己的手机，这种做法正日益流行。如今智能手机功能也越来越多，我们不仅能用自己的手机访问电脑、网...[详细]
SMT贴片机是表面贴装技术（Surface Mount Technology）中的重要设备，它的性能状态对电子制造的质量和效率有着决定性的影响。因此，对SMT贴片机的主要指标性能进行定期检测非常重要。以下是一些主要的检测项目： 定位精度：定位精度是SMT贴片机的核心性能指标，它直接影响到贴片的准确性。通常，我们通过重复测量贴片机在X、Y轴上的移动误差来检测其定位精度。 贴片速度：贴片速度...[详细]
嵌入式系统
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
